 | 2011 |
|---|
| 12 |       | Zuow-Zun Chen,
Tai-Cheng Lee:
The Design and Analysis of Dual-Delay-Path Ring Oscillators.
IEEE Trans. on Circuits and Systems 58-I(3): 470-478 (2011) |
| 11 | | Yen-Chuan Huang,
Tai-Cheng Lee:
A 10-bit 100-MS/s 4.5-mW Pipelined ADC With a Time-Sharing Technique.
IEEE Trans. on Circuits and Systems 58-I(6): 1157-1166 (2011) |
| 10 | | Zuow-Zun Chen,
Tai-Cheng Lee:
The Study of a Dual-Mode Ring Oscillator.
IEEE Trans. on Circuits and Systems 58-II(4): 210-214 (2011) |
| 2010 |
|---|
| 9 | | Chin-Yu Lin,
Chun-Yu Chiang,
Tai-Cheng Lee:
An offset phase-locked loop spread spectrum clock generator for SATA III.
CICC 2010: 1-4 |
| 8 | | Yen-Chuan Huang,
Tai-Cheng Lee:
A 10b 100MS/s 4.5mW pipelined ADC with a time sharing technique.
ISSCC 2010: 300-301 |
| 7 | | Tai-Cheng Lee,
Cheng-Hsiao Lin:
Nonlinear R-2R Transistor-Only DAC.
IEEE Trans. on Circuits and Systems 57-I(10): 2644-2653 (2010) |
| 6 | | Yen-Chuan Huang,
Tai-Cheng Lee:
A 0.02-mm 2 9-Bit 50-MS/s Cyclic ADC in 90-nm Digital CMOS Technology.
J. Solid-State Circuits 45(3): 610-619 (2010) |
| 2009 |
|---|
| 5 | | Li-Han Hung,
Tai-Cheng Lee:
A Split-Based Digital Background Calibration Technique in Pipelined ADCs.
IEEE Trans. on Circuits and Systems 56-II(11): 855-859 (2009) |
| 2005 |
|---|
| 4 | | Ding-Lan Shen,
Tai-Cheng Lee:
A linear-approximation technique for digitally-calibrated pipelined A/D converters.
ISCAS (2) 2005: 1382-1385 |
| 3 | | Tai-Cheng Lee,
Yen-Chuan Huang:
An optimization technique for RF buffers with active inductors.
ISCAS (4) 2005: 3692-3695 |
| 2004 |
|---|
| 2 |  | Hung-Chieh Tsai,
Jyh-Yih Yeh,
Wei-Hsuan Tu,
Tai-Cheng Lee,
Chorng-Kuang Wang:
A 10 Gbase-LX4 receiver front end transimpedance amplifier and limiting amplifier.
ISCAS (4) 2004: 393-396 |
| 2002 |
|---|
| 1 | | Chih-Chun Tang,
Chia-Hsin Wu,
Kun-Hsien Li,
Tai-Cheng Lee,
Shen-Iuan Liu:
CMOS 2.4-GHz receiver front end with area-efficient inductors and digitally calibrated 90° delay network.
ISCAS (3) 2002: 77-80 |
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