Kuen-Jong Lee

	2012
60		Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer: Efficient Overdetection Elimination of Acceptable Faults for Yield Improvement. IEEE Trans. on CAD of Integrated Circuits and Systems 31(5): 754-764 (2012)
	2011
59		Kuen-Jong Lee, Chin-Yao Chang, I.-Jou Chen: EPIDETOX: an ESL platform for integrated circuit design and tool exploration. CODES+ISSS 2011: 381-384
58		Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee: Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores. IEEE Trans. VLSI Syst. 19(3): 516-520 (2011)
57		Kuen-Jong Lee, Wei-Cheng Lien, Tong-Yu Hsieh: Test Response Compaction via Output Bit Selection. IEEE Trans. on CAD of Integrated Circuits and Systems 30(10): 1534-1544 (2011)
56		Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer: An Error-Tolerance-Based Test Methodology to Support Product Grading for Yield Enhancement. IEEE Trans. on CAD of Integrated Circuits and Systems 30(6): 930-934 (2011)
	2010
55		Wei-Cheng Lien, Kuen-Jong Lee: A Complete Logic BIST Technology with No Storage Requirement. Asian Test Symposium 2010: 129-134
54		Kuen-Jong Lee, Tong-Yu Hsieh, Chin-Yao Chang, Yu-Ting Hong, Wen-Cheng Huang: On-Chip SOC Test Platform Design Based on IEEE 1500 Standard. IEEE Trans. VLSI Syst. 18(7): 1134-1139 (2010)
	2009
53		Chin-Yao Chang, Chih-Yuan Hsiao, Kuen-Jong Lee, Alan P. Su: Transaction Level Modeling and Design Space Exploration for SOC Test Architectures. Asian Test Symposium 2009: 200-205
52		Jing-Wun Lin, Chen-Chieh Wang, Chin-Yao Chang, Chung-Ho Chen, Kuen-Jong Lee, Yuan-Hua Chu, Jen-Chieh Yeh, Ying-Chuan Hsiao: Full System Simulation and Verification Framework. IAS 2009: 165-168
51		Tong-Yu Hsieh, Melvin A. Breuer, Murali Annavaram, Sandeep K. Gupta, Kuen-Jong Lee: Tolerance of performance degrading faults for effective yield improvement. ITC 2009: 1-10
50		Kuen-Jong Lee, Si-Yuan Liang, Alan P. Su: A low-cost SOC debug platform based on on-chip test architectures. SoCC 2009: 161-164
49		Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Wen-Ben Jone, Jianghao Guo, Kuen-Jong Lee, Wei-Shin Wang, Xiaoqing Wen, Hao-Jan Chao, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li: Turbo1500: Core-Based Design for Test and Diagnosis. IEEE Design & Test of Computers 26(1): 26-35 (2009)
	2008
48		Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee: A hybrid self-testing methodology of processor cores. ISCAS 2008: 3378-3381
47		Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Kuen-Jong Lee, Xiaoqing Wen, Wen-Ben Jone, Chia-Hsien Yeh, Wei-Shin Wang, Hao-Jan Chao, Jianghao Guo, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li: Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard. ITC 2008: 1-9
46		Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee: A hybrid software-based self-testing methodology for embedded processor. SAC 2008: 1528-1534
45		Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer: An Error Rate Based Test Methodology to Support Error-Tolerance. IEEE Transactions on Reliability 57(1): 204-214 (2008)
	2007
44		Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer: Reduction of detected acceptable faults for yield improvement via error-tolerance. DATE 2007: 1599-1604
	2006
43		Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer: An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance. VTS 2006: 130-135
	2005
42		Kuen-Jong Lee, Chia-Yi Chu, Yu-Ting Hong: An embedded processor based SOC test platform. ISCAS (3) 2005: 2983-2986
41		Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer: A novel test methodology based on error-rate to support error-tolerance. ITC 2005: 9
	2004
40		Kuen-Jong Lee, Shaing-Jer Hsu, Chia-Ming Ho: Test Power Reduction with Multiple Capture Orders. Asian Test Symposium 2004: 26-31
39		Chih-Haur Huang, Kuen-Jong Lee, Soon-Jyh Chang: A Low-Cost Diagnosis Methodology for Pipelined A/D Converters. Asian Test Symposium 2004: 296-301
	2003
38		Kuen-Jong Lee, Soon-Jyh Chang, Ruei-Shiuan Tzeng: A Sigma-Delta Modulation Based BIST Scheme for A/D Converters. Asian Test Symposium 2003: 124-129
37		Jih-Jeen Chen, Chia-Kai Yang, Kuen-Jong Lee: Test pattern generation and clock disabling for simultaneous test time and power reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 363-370 (2003)
	2002
36		Kuen-Jong Lee, Jih-Jeen Chen: Reducing Test Application Time and Power Dissipation for Scan-Based Testing via Multiple Clock Disabling. Asian Test Symposium 2002: 338-
35		Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee: An efficient BIST method for distributed small buffers. IEEE Trans. VLSI Syst. 10(4): 512-515 (2002)
34		Kuen-Jong Lee, Chau-chin Su: Guest Editorial. J. Electronic Testing 18(1): 15-16 (2002)
33		Wei-Lun Wang, Kuen-Jong Lee: An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment. J. Electronic Testing 18(1): 43-53 (2002)
32		Kuen-Jong Lee, Tsung-Chu Huang: An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application. J. Electronic Testing 18(6): 627-636 (2002)
	2001
31		Tsung-Chu Huang, Kuen-Jong Lee: A Low-Power LFSR Architecture. Asian Test Symposium 2001: 470
30		Tsung-Chu Huang, Kuen-Jong Lee: A token scan architecture for low power testing. ITC 2001: 660-669
29		Wei-Lun Wang, Kuen-Jong Lee, Jhing-Fa Wang: An on-chip march pattern generator for testing embedded memory cores. IEEE Trans. VLSI Syst. 9(5): 730-735 (2001)
28		Yun-Che Wen, Kuen-Jong Lee: Analysis and generation of control and observation structures foranalog circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 165-171 (2001)
27		Tsung-Chu Huang, Kuen-Jong Lee: Reduction of power consumption in scan-based circuits during testapplication by an input control technique. IEEE Trans. on CAD of Integrated Circuits and Systems 20(7): 911-917 (2001)
	2000
26		Kuen-Jong Lee, Cheng-I. Huang: A hierarchical test control architecture for core based design. Asian Test Symposium 2000: 248-253
25		Wei-Lun Wang, Kuen-Jong Lee: Accelerated test pattern generators for mixed-mode BIST environments. Asian Test Symposium 2000: 368-373
24		Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen: Peak-power reduction for multiple-scan circuits during test application. Asian Test Symposium 2000: 453-458
23		Yun-Che Wen, Kuen-Jong Lee: An on Chip ADC Test Structure. DATE 2000: 221-225
	1999
22		Tsung-Chu Huang, Kuen-Jong Lee: An Input Control Technique for Power Reduction in Scan Circuits During Test Application. Asian Test Symposium 1999: 315-320
21		Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee: An Efficient BIST Method for Small Buffers. VTS 1999: 246-251
20		Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang: BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults. ACM Trans. Design Autom. Electr. Syst. 4(2): 194-218 (1999)
19		Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang: Broadcasting test patterns to multiple circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 18(12): 1793-1802 (1999)
	1998
18		Kuen-Jong Lee, Jing-Jou Tang, Wern-Yih Duh: On the Determination of Threshold Voltages for CMOS Gates to Facilitate Test Pattern Generation and Fault Simulation. Asian Test Symposium 1998: 113-118
17		Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang: Using a single input to support multiple scan chains. ICCAD 1998: 74-78
16		Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu: A graph representation for programmable logic arrays to facilitate testing and logic design. IEEE Trans. on CAD of Integrated Circuits and Systems 17(10): 1030-1043 (1998)
15		Kuen-Jong Lee, Wei-Lun Wang, Jhing-Fa Wang: A General Structure of Feedback Shift Registers for Built-In Self Test. J. Inf. Sci. Eng. 14(3): 645-667 (1998)
14		Kuen-Jong Lee, Cheng-Hsuing Kuo: Concurrent Error Detection, Diagnosis, and Fault Tolerance for Switched-Capacitor Filters. J. Inf. Sci. Eng. 14(4): 863-890 (1998)
	1997
13		Tsung-Chu Huang, Min-Cheng Huang, Kuen-Jong Lee: Built-in current sensor designs based on the bulk-driven technique. Asian Test Symposium 1997: 384-
	1996
12		Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai: Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults. Asian Test Symposium 1996: 100-
11		Kuen-Jong Lee, Jing-Jou Tang: Two Modeling Techniques For CMOS Circuits To Enhance Test Generation And Fault Simulation For Bridging Faults. Asian Test Symposium 1996: 165-171
	1995
10		Jing-Jou Tang, Bin-Da Liu, Kuen-Jong Lee: An IDDQ Fault Model to Facilitate the Design of Built-In Current Sensor (BICSs). ISCAS 1995: 393-396
9		Kuen-Jong Lee, Sheng-Yih Jeng, Tian-Pao Lee: A New Architecture for Analog Boundary Scan. ISCAS 1995: 409-412
8		Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu: A practical current sensing technique for IDDQ testing. IEEE Trans. VLSI Syst. 3(2): 302-310 (1995)
7		Kuen-Jong Lee, Chih-Nan Wang, Rajiv Gupta, Melvin A. Breuer: An integrated system for assigning signal flow directions to CMOS transistors. IEEE Trans. on CAD of Integrated Circuits and Systems 14(12): 1445-1458 (1995)
	1994
6		Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer: SWiTEST: a switch level test generation system for CMOS combinational circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 13(5): 625-637 (1994)
	1992
5		Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer: SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits. DAC 1992: 26-29
4		Wei-Lun Wang, Jhing-Fa Wang, Kuen-Jong Lee: A Fast Testing Method for Sequential Circuits at the State Trasition Level. ITC 1992: 514-519
3		Kuen-Jong Lee, Melvin A. Breuer: Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults. IEEE Trans. on CAD of Integrated Circuits and Systems 11(5): 659-670 (1992)
	1990
2		Kuen-Jong Lee, Rajiv Gupta, Melvin A. Breuer: A New Method for Assigning Signal Flow Directions to MOS Transistors. ICCAD 1990: 492-495
1		Kuen-Jong Lee, Melvin A. Breuer: On the charge sharing problem in CMOS stuck-open fault testing. ITC 1990: 417-426

Coauthor Index

1	Murali Annavaram	[51]
2	Ravi Apte	[47] [49]
3	Melvin A. Breuer	[1] [2] [3] [5] [6] [7] [41] [43] [44] [45] [51] [56] [60]
4	Chin-Yao Chang	[52] [53] [54] [59]
5	Soon-Jyh Chang	[38] [39]
6	Hao-Jan Chao	[47] [49]
7	Chung-Ho Chen	[46] [48] [52] [58]
8	I.-Jou Chen	[59]
9	Jih-Jeen Chen	[17] [19] [24] [36] [37]
10	Chia-Yi Chu	[42]
11	Yuan-Hua Chu	[52]
12	Wern-Yih Duh	[18]
13	Jianghao Guo	[47] [49]
14	Rajiv Gupta	[2] [7]
15	Sandeep K. Gupta	[51]
16	Chia-Ming Ho	[40]
17	Yu-Ting Hong	[42] [54]
18	Chih-Yuan Hsiao	[53]
19	Ying-Chuan Hsiao	[52]
20	Tong-Yu Hsieh	[41] [43] [44] [45] [51] [54] [56] [57] [60]
21	Shaing-Jer Hsu	[40]
22	Cheng-Hua Huang	[17] [19]
23	Cheng-I. Huang	[26]
24	Chih-Haur Huang	[39]
25	Der-Cheng Huang	[21] [35]
26	Min-Cheng Huang	[13]
27	Tsung-Chu Huang	[12] [13] [20] [22] [24] [27] [30] [31] [32]
28	Wen-Cheng Huang	[54]
29	Sheng-Yih Jeng	[9]
30	Wen-Ben Jone	[21] [35] [47] [49]
31	Cheng-Hsuing Kuo	[14]
32	Tian-Pao Lee	[9]
33	Fangfang Li	[47] [49]
34	Si-Yuan Liang	[50]
35	Wei-Cheng Lien	[55] [57]
36	Jing-Wun Lin	[52]
37	Bin-Da Liu	[8] [10] [16]
38	Jinsong Liu	[47] [49]
39	Tai-Hua Lu	[46] [48] [58]
40	Yanlong Niu	[47] [49]
41	Charles Njinda	[5] [6]
42	Boryau Sheu	[47] [49]
43	Alan P. Su	[50] [53]
44	Chau-chin Su	[34]
45	Yi-Chih Sung	[47] [49]
46	Jing-Jou Tang	[8] [10] [11] [12] [16] [18] [20]
47	Cheng-Liang Tsai	[12]
48	Ruei-Shiuan Tzeng	[38]
49	Chen-Chieh Wang	[52]
50	Chi-Chun Wang	[47] [49]
51	Chih-Nan Wang	[7]
52	Jhing-Fa Wang	[4] [15] [29]
53	Laung-Terng Wang	[47] [49]
54	Wei-Lun Wang	[4] [15] [25] [29] [33]
55	Wei-Shin Wang	[47] [49]
56	Xiaoqing Wen	[47] [49]
57	Yun-Che Wen	[23] [28]
58	S. C. Wu	[21] [35]
59	Shianling Wu	[47] [49]
60	Chia-Kai Yang	[37]
61	Chia-Hsien Yeh	[47]
62	Jen-Chieh Yeh	[52]

Colors in the list of coauthors

Last update Fri Jun 1 15:44:53 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page