 | 2011 |
|---|
| 9 |       | Naifeng Jing,
Ju-Yueh Lee,
Chun Zhang,
Jiarong Tong,
Zhigang Mao,
Lei He:
Fault modeling and characteristics of SRAM-based FPGAs (abstract only).
FPGA 2011: 279 |
| 8 | | Naifeng Jing,
Ju-Yueh Lee,
Zhe Feng,
Weifeng He,
Zhigang Mao,
Shi-Jie Wen,
Rick Wong,
Lei He:
Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms.
FPL 2011: 282-285 |
| 7 | | Naifeng Jing,
Ju-Yueh Lee,
Weifeng He,
Zhigang Mao,
Lei He:
Mitigating FPGA interconnect soft errors by in-place LUT inversion.
ICCAD 2011: 582-586 |
| 6 | | Wenyao Xu,
Jia Wang,
Yu Hu,
Ju-Yueh Lee,
Fang Gong,
Lei He,
Majid Sarrafzadeh:
In-Place FPGA Retiming for Mitigation of Variational Single-Event Transient Faults.
IEEE Trans. on Circuits and Systems 58-I(6): 1372-1381 (2011) |
| 2010 |
|---|
| 5 | | Ju-Yueh Lee,
Yu Hu,
Rupak Majumdar,
Lei He,
Minming Li:
Fault-tolerant resynthesis with dual-output LUTs.
ASP-DAC 2010: 325-330 |
| 4 | | Samuel B. Luckenbill,
Ju-Yueh Lee,
Yu Hu,
Rupak Majumdar,
Lei He:
RALF: Reliability Analysis for Logic Faults - An exact algorithm and its applications.
DATE 2010: 783-788 |
| 3 | | Ju-Yueh Lee,
Zhe Feng,
Lei He:
In-place decomposition for robustness in FPGA.
ICCAD 2010: 143-148 |
| 2009 |
|---|
| 2 | | Ju-Yueh Lee,
Yu Hu,
Rupak Majumdar,
Lei He:
Simultaneous test pattern compaction, ordering and X-filling for testing power reduction.
ISQED 2009: 702-707 |
| 2006 |
|---|
| 1 | | Kun-Lin Tsai,
Ju-Yueh Lee,
Shanq-Jang Ruan,
Feipei Lai:
Low power scheduling method using multiple supply voltages.
ISCAS 2006 |
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