Jooheung Lee

	2012
15		Rakan Khraisha, Jooheung Lee: A Bit-Rate Aware Scalable H.264/AVC Deblocking Filter Using Dynamic Partial Reconfiguration. Signal Processing Systems 66(3): 225-234 (2012)
	2011
14		Jian Huang, Jooheung Lee: Reconfigurable Architecture for ZQDCT Using Computational Complexity Prediction and Bitstream Relocation. Embedded Systems Letters 3(1): 1-4 (2011)
	2010
13		Toomas P. Plaks, David Andrews, Ronald F. DeMara, Herman Lam, Jooheung Lee, Christian Plessl, Greg Stitt: Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2010, July 12-15, 2010, Las Vegas Nevada, USA CSREA Press 2010
12		Ronald F. DeMara, Jooheung Lee, Rawad N. Al-Haddad, Rashad S. Oreifej, Rizwan Ashraf, Brian Stensrud, Michael Quist: Dynamic Partial Reconfiguration Approach to the Design of Sustainable Edge Detectors. ERSA 2010: 49-58
11		Rakan Khraisha, Jooheung Lee: A scalable H.264/AVC deblocking filter architecture using dynamic partial reconfiguration. ICASSP 2010: 1566-1569
	2009
10		Sumedha Gupta Kodipyaka, Jooheung Lee: A Scalable H.264/AVC Variable Block Size Motion Estimation Engine Using Partial Reconfiguration. ERSA 2009: 219-225
9		Jian Huang, Jooheung Lee: A Self-Reconfigurable Platform for Scalable DCT Computation Using Compressed Partial Bitstreams and BlockRAM Prefetching. ISVLSI 2009: 67-72
8		Jian Huang, Matthew Parris, Jooheung Lee, Ronald F. DeMara: Scalable FPGA-based architecture for DCT computation using dynamic partial reconfiguration. ACM Trans. Embedded Comput. Syst. 9(1): (2009)
7		Jian Huang, Jooheung Lee: A Self-Reconfigurable Platform for Scalable DCT Computation Using Compressed Partial Bitstreams and BlockRAM Prefetching. IEEE Trans. Circuits Syst. Video Techn. 19(11): 1623-1632 (2009)
	2008
6		Jian Huang, Matthew Parris, Jooheung Lee, Ronald F. DeMara: Scalable FPGA Architecture for DCT Computation Using Dynamic Partial Reconfiguration. ERSA 2008: 269-272
5		Yidong Liu, Srinivasan Santhanam, Jooheung Lee: Performance Evaluation of FPGA-based Hardware Accelerator: A Case Study. ERSA 2008: 313-314
4		Jian Huang, Jooheung Lee, Hao Li: A Fast FPGA Implementation of Tate Pairing in Cryptography over Binary Field. Security and Management 2008: 3-9
	2006
3		Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne Wolf: An efficient architecture for motion estimation and compensation in the transform domain. IEEE Trans. Circuits Syst. Video Techn. 16(2): 191-201 (2006)
2		Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin: Inverse discrete cosine transform architecture exploiting sparseness and symmetry properties. IEEE Trans. Circuits Syst. Video Techn. 16(5): 655-662 (2006)
1		Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, Rajarathnam Chandramouli: Block-based frequency scalable technique for efficient hierarchical coding. IEEE Transactions on Signal Processing 54(7): 2559-2566 (2006)

Coauthor Index

1	Rawad N. Al-Haddad	[12]
2	David Andrews	[13]
3	Rizwan Ashraf	[12]
4	Rajarathnam Chandramouli	[1]
5	Ronald F. DeMara	[6] [8] [12] [13]
6	Jian Huang	[4] [6] [7] [8] [9] [14]
7	Mary Jane Irwin	[1] [2] [3]
8	Rakan Khraisha	[11] [15]
9	Sumedha Gupta Kodipyaka	[10]
10	Herman Lam	[13]
11	Hao Li	[4]
12	Yidong Liu	[5]
13	Rashad S. Oreifej	[12]
14	Matthew Parris	[6] [8]
15	Toomas P. Plaks	[13]
16	Christian Plessl	[13]
17	Michael Quist	[12]
18	Srinivasan Santhanam	[5]
19	Brian Stensrud	[12]
20	Greg Stitt	[13]
21	Narayanan Vijaykrishnan (Vijaykrishnan Narayanan)	[1] [2] [3]
22	Marilyn Wolf (Wayne Wolf, Wayne Hendrix Wolf)	[3]

Colors in the list of coauthors

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