 | 2011 |
| 11 |  | Parimala Thulasiraman,
Laurence Tianruo Yang,
Qiwen Pan,
Xingang Liu,
Yaw-Chung Chen,
Yo-Ping Huang,
Lin-huang Chang,
Che-Lun Hung,
Che-Rung Lee,
Justin Y. Shi,
Ying Zhang:
13th IEEE International Conference on High Performance Computing & Communication, HPCC 2011, Banff, Alberta, Canada, September 2-4, 2011
IEEE 2011 |
| 10 |  | Shih-Hsiang Lo,
Che-Rung Lee,
Yeh-Ching Chung,
I-Hsin Chung:
A Parallel Rectangle Intersection Algorithm on GPU+CPU.
CCGRID 2011: 43-52 |
| 9 |  | Po-Chi Shih,
Kuo-Chan Huang,
Che-Rung Lee,
I-Hsin Chung,
Yeh-Ching Chung:
A Performance Goal Oriented Processor Allocation Technique for Centralized Heterogeneous Multi-cluster Environments.
CCGRID 2011: 614-615 |
| 8 |  | I-Hsin Chung,
Che-Rung Lee,
Jiazheng Zhou,
Yeh-Ching Chung:
Scalable Communication-Aware Task Mapping Algorithms for Interconnected Multicore Systems.
HPCC 2011: 759-764 |
| 7 |  | Chung-Han Chou,
Nien-Yu Tsai,
Hao Yu,
Che-Rung Lee,
Yiyu Shi,
Shih-Chieh Chang:
On the preconditioner of conjugate gradient method - A power grid simulation perspective.
ICCAD 2011: 494-497 |
| 6 |  | Che-Rung Lee,
Zhaojun Bai:
Redesign of Higher-Level Matrix Algorithms for Multicore and Distributed Architectures and Applications in Quantum Monte Carlo Simulation.
IPDPS 2011: 266-274 |
| 5 |  | I-Hsin Chung,
Che-Rung Lee,
Jiazheng Zhou,
Yeh-Ching Chung:
Hierarchical Mapping for HPC Applications.
IPDPS Workshops 2011: 1815-1823 |
| 4 |  | I-Hsin Chung,
Che-Rung Lee,
Jiazheng Zhou,
Yeh-Ching Chung:
Hierarchical Mapping for HPC Applications.
Parallel Processing Letters 21(3): 279-299 (2011) |
| 2010 |
| 3 |  | Che-Rung Lee,
I-Hsin Chung,
Zhaojun Bai:
Parallelization of DQMC simulation for strongly correlated electron systems.
IPDPS 2010: 1-9 |
| 2008 |
| 2 |  | Che-Rung Lee,
G. W. Stewart:
Algorithm 879: EIGENTEST - a test matrix generator for large-scale eigenproblems.
ACM Trans. Math. Softw. 35(1): (2008) |
| 2000 |
| 1 |  | Wei Kuan Shih,
Che-Rung Lee,
Ching-Hui Tang:
A Fast Algorithm for Scheduling Imprecise Computations with Timing Constraints to Minimize Weighted Error.
IEEE Real-Time Systems Symposium 2000: 305-310 |