 | 2009 |
|---|
| 5 |       | Jaesung Lee,
Hyuk-Jae Lee,
Chanho Lee:
A Phase-Based Approach for On-Chip Bus Architecture Optimization.
Comput. J. 52(6): 626-645 (2009) |
| 2007 |
|---|
| 4 | | Jaesung Lee,
Hyuk-Jae Lee,
Chanho Lee:
A High-Speed Link Layer Architecture for Low Latency and Memory Cost Reduction.
Comput. J. 50(5): 616-628 (2007) |
| 2006 |
|---|
| 3 | | Sanghun Lee,
Chanho Lee:
A High Performance SoC On-chip-bus with Multiple Channels and Routing Processes.
VLSI-SoC 2006: 86-91 |
| 2005 |
|---|
| 2 | | Kyu-Il Lee,
Chanho Lee,
Hyungsoon Shin,
Young June Park,
Hong Shick Min:
Efficient frequency-domain simulation technique for short-channel MOSFET.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 862-868 (2005) |
| 2004 |
|---|
| 1 | | Jae-Sun Han,
Tae-Jin Kim,
Chanho Lee:
High performance Viterbi decoder using modified register exchange methods.
ISCAS (3) 2004: 553-556 |
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