Per Larsson-Edefors

	2011
46		E. Ryman, A. Emrich, S. Andersson, J. Riesbeck, Lars J. Svensson, Per Larsson-Edefors: 3.6-GHz 0.2-mW/ch/GHz 65-nm cross-correlator for synthetic aperture radiometry. CICC 2011: 1-4
45		Alen Bardizbanyan, Magnus Själander, Per Larsson-Edefors: Reconfigurable Instruction Decoding for a Wide-Control-Word Processor. IPDPS Workshops 2011: 322-325
44		Babak Hidaji, Salar Alipour, Kasyab P. Subramaniyan, Per Larsson-Edefors: Application-Specific Energy Optimization of General-Purpose Datapath Interconnect. ISVLSI 2011: 301-306
	2010
43		Lars J. Svensson, Johnny Pihl, Daniel A. Andersson, Per Larsson-Edefors: On-chip power supply noise and its implications on timing. ACM Great Lakes Symposium on VLSI 2010: 389-392
42		Tung Thanh Hoang, Ulf Jalmbrant, Erik der Hagopian, Kasyab P. Subramaniyan, Magnus Själander, Per Larsson-Edefors: Design space exploration for an embedded processor with flexible datapath interconnect. ASAP 2010: 55-62
41		Muhammad Waqar Azhar, Tung Thanh Hoang, Per Larsson-Edefors: Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor. DSD 2010: 675-680
40		Alen Bardizbanyan, Kasyab P. Subramaniyan, Per Larsson-Edefors: Generation and Exploration of Layouts for Area-Efficient Barrel Shifters. ISVLSI 2010: 454-455
39		Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors: A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit. IEEE Trans. on Circuits and Systems 57-I(12): 3073-3081 (2010)
	2009
38		Patrik Kimfors, Niklas Broman, Andreas Haraldsson, Kasyab P. Subramaniyan, Magnus Själander, Henrik Eriksson, Per Larsson-Edefors: Custom layout strategy for rectangle-shaped log-depth multiplier reduction tree. ICECS 2009: 77-80
37		Kasyab P. Subramaniyan, Emil Axelsson, Per Larsson-Edefors, Mary Sheeran: Layout exploration of geometrically accurate arithmetic circuits. ICECS 2009: 795-798
36		Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors: Double Throughput Multiply-Accumulate unit for FlexCore processor enhancements. IPDPS 2009: 1-7
35		Thomas Schilling, Magnus Själander, Per Larsson-Edefors: Scheduling for an Embedded Architecture with a Flexible Datapath. ISVLSI 2009: 151-156
34		Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors: High-speed, energy-efficient 2-cycle Multiply-Accumulate architecture. SoCC 2009: 119-122
33		Magnus Själander, Per Larsson-Edefors: Multiplication Acceleration Through Twin Precision. IEEE Trans. VLSI Syst. 17(9): 1233-1246 (2009)
32		Martin Thuresson, Magnus Själander, Magnus Björk, Lars J. Svensson, Per Larsson-Edefors, Per Stenström: FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. Signal Processing Systems 57(1): 5-19 (2009)
	2008
31		Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors: Noise-Aware On-Chip Power Grid Considerations Using a Statistical Approach. ISQED 2008: 663-669
30		Daniel A. Andersson, Simon Kristiansson, Lars J. Svensson, Per Larsson-Edefors, Kjell O. Jeppson: Noise Interaction Between Power Distribution Grids and Substrate. ISQED 2008: 84-89
29		Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors: Time-domain interconnect characterisation flow for appropriate model segmentation. IET Computers & Digital Techniques 2(4): 265-274 (2008)
	2007
28		Minh Quang Do, Per Larsson-Edefors, Mindaugas Drazdziulis: High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process. DSD 2007: 249-256
27		Martin Thuresson, Magnus Själander, Magnus Björk, Lars J. Svensson, Per Larsson-Edefors, Per Stenström: FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. ICSAMOS 2007: 18-25
26		Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson: Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays. ISQED 2007: 185-191
25		Mindaugas Drazdziulis, Per Larsson-Edefors, Lars J. Svensson: Overdrive Power-Gating Techniques for Total Power Minimization. ISVLSI 2007: 125-132
24		Magnus Själander, Per Larsson-Edefors, Magnus Björk: A Flexible Datapath Interconnect for Embedded Applications. ISVLSI 2007: 15-20
	2006
23		Henrik Eriksson, Per Larsson-Edefors, Mary Sheeran, Magnus Själander, D. Johansson, M. Scholin: Multiplier reduction tree with logarithmic logic depth and regular connectivity. ISCAS 2006
22		Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson: Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration. ISQED 2006: 557-563
21		Henrik Eriksson, Per Larsson-Edefors, Daniel Eckerbert: Toward architecture-based test-vector generation for timing verification of fast parallel multipliers. IEEE Trans. VLSI Syst. 14(4): 370-379 (2006)
	2005
20		Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors: Accounting for the skin effect during repeater insertion. ACM Great Lakes Symposium on VLSI 2005: 32-37
19		Magnus Själander, Mindaugas Drazdziulis, Per Larsson-Edefors, Henrik Eriksson: A low-leakage twin-precision multiplier using reconfigurable power gating. ISCAS (2) 2005: 1654-1657
	2004
18		Magnus Själander, Henrik Eriksson, Per Larsson-Edefors: An Efficient Twin-Precision Multiplier. ICCD 2004: 30-33
17		Henrik Eriksson, Per Larsson-Edefors: Glitch-conscious low-power design of arithmetic circuits. ISCAS (2) 2004: 281-284
16		Henrik Eriksson, Per Larsson-Edefors: Dynamic pass-transistor dot operators for efficient parallel-prefix adders. ISCAS (2) 2004: 461-464
15		Mindaugas Drazdziulis, Per Larsson-Edefors: Evaluation of power cut-off techniques in the presence of gate leakage. ISCAS (2) 2004: 745-748
14		Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors: On Skin Effect in On-Chip Interconnects. PATMOS 2004: 463-470
13		Minh Quang Do, Per Larsson-Edefors, Lars Bengtsson: Table-Based Total Power Consumption Estimation of Memory Arrays for Architects. PATMOS 2004: 869-878
12		Dainius Ciuplys, Per Larsson-Edefors: On Maximum Current Estimation in CMOS Digital Circuits. VLSI Design 2004: 658-661
	2003
11		Minh Quang Do, Lars Bengtsson, Per Larsson-Edefors: DSP-PP: A Simulator/Estimator of Power Consumption and Performance for Parallel DSP Architectures. Applied Informatics 2003: 767-772
10		Daniel Eckerbert, Lars J. Svensson, Per Larsson-Edefors: A Mixed-Mode Delay-Locked-Loop Architecture. ICCD 2003: 261-263
9		Per Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson, Lars J. Svensson: Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects. ISVLSI 2003: 225-230
	2001
8		Daniel Eckerbert, Per Larsson-Edefors: Interconnect-Driven Short-Circuit Power Modeling. DSD 2001: 414-421
7		Henrik Eriksson, Per Larsson-Edefors, William P. Marnane: A regular parallel multiplier which utilizes multiple carry-propagate adders. ISCAS (4) 2001: 166-169
6		Henrik Eriksson, Per Larsson-Edefors, Atila Alvandpour: A 2.8 ns 30 uW/MHz area-efficient 32-b Manchester carry-bypass adder. ISCAS (4) 2001: 84-87
5		Daniel Eckerbert, Per Larsson-Edefors: Cycle-true leakage current modeling for CMOS gates. ISCAS (5) 2001: 507-510
	2000
4		Henrik Eriksson, Per Larsson-Edefors: Impact of Voltage Scaling on Glitch Power Consumption. PATMOS 2000: 139-148
	1998
3		Per Larsson-Edefors: A Miniature Serial-Data SIMD Architecture. EUROMICRO 1998: 10341-10344
2		Atila Alvandpour, Per Larsson-Edefors, Christer Svensson: Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits. ISLPED 1998: 245-249
	1996
1		Per Larsson-Edefors: Technology mapping onto very-high-speed standard CMOS hardware. IEEE Trans. on CAD of Integrated Circuits and Systems 15(9): 1137-1144 (1996)

Coauthor Index

1	Salar Alipour	[44]
2	Atila Alvandpour	[2] [6]
3	Daniel A. Andersson	[14] [20] [29] [30] [31] [43]
4	S. Andersson	[46]
5	Emil Axelsson	[37]
6	Muhammad Waqar Azhar	[41]
7	Alen Bardizbanyan	[40] [45]
8	Lars Bengtsson	[11] [13] [22] [26]
9	Magnus Björk	[24] [27] [32]
10	Niklas Broman	[38]
11	Dainius Ciuplys	[12]
12	Minh Quang Do	[11] [13] [22] [26] [28]
13	Mindaugas Drazdziulis	[15] [19] [22] [25] [26] [28]
14	Daniel Eckerbert	[5] [8] [9] [10] [21]
15	A. Emrich	[46]
16	Henrik Eriksson	[4] [6] [7] [9] [16] [17] [18] [19] [21] [23] [38]
17	Erik der Hagopian	[42]
18	Andreas Haraldsson	[38]
19	Babak Hidaji	[44]
20	Tung Thanh Hoang	[34] [36] [39] [41] [42]
21	Ulf Jalmbrant	[42]
22	Kjell O. Jeppson	[30]
23	D. Johansson	[23]
24	Patrik Kimfors	[38]
25	Simon Kristiansson	[30]
26	William P. Marnane (Liam Marnane)	[7]
27	Johnny Pihl	[43]
28	J. Riesbeck	[46]
29	E. Ryman	[46]
30	Thomas Schilling	[35]
31	M. Scholin	[23]
32	Mary Sheeran	[23] [37]
33	Magnus Själander	[18] [19] [23] [24] [27] [32] [33] [34] [35] [36] [38] [39] [42] [45]
34	Per Stenström	[27] [32]
35	Kasyab P. Subramaniyan	[37] [38] [40] [42] [44]
36	Christer Svensson	[2]
37	Lars J. Svensson	[9] [10] [14] [20] [25] [27] [29] [30] [31] [32] [43] [46]
38	Martin Thuresson	[27] [32]

Colors in the list of coauthors

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