 | 2011 |
|---|
| 3 |       | Chang-Ming Lai,
Meng-Hung Shen,
Yi-Da Wu,
Kai-Hsiang Huang,
Po-Chiun Huang:
A 0.24 to 2.4 GHz phase-locked loop with low supply sensitivity in 0.18-µm CMOS.
ISCAS 2011: 981-984 |
| 2010 |
|---|
| 2 | | Yi-Da Wu,
Chang-Ming Lai,
Chao-Cheng Lee,
Po-Chiun Huang:
A Quantization Error Minimization Method Using DDS-DAC for Wideband Fractional-N Frequency Synthesizer.
J. Solid-State Circuits 45(11): 2283-2291 (2010) |
| 2006 |
|---|
| 1 | | Yi-Da Wu,
Chang-Ming Lai,
Chih-Yuan Chou,
Po-Chiun Huang:
An OPLL-DDS based frequency synthesizer for DCS-1800 receiver.
ISCAS 2006 |
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