 | 2012 |
|---|
| 6 |       | Sewook Hwang,
Minyoung Song,
Young-Ho Kwak,
Inhwa Jung,
Chulwoo Kim:
A 3.5 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modulation Profile.
J. Solid-State Circuits 47(5): 1199-1208 (2012) |
| 2011 |
|---|
| 5 | | Sewook Hwang,
Minyoung Song,
Young-Ho Kwak,
Inhwa Jung,
Chulwoo Kim:
A 0.076mm2 3.5GHz spread-spectrum clock generator with memoryless Newton-Raphson modulation profile in 0.13μm CMOS.
ISSCC 2011: 360-362 |
| 4 | | Sang-Yoon Lee,
Hyung-Rok Lee,
Young-Ho Kwak,
Woo-Seok Choi,
Byoung-Joo Yoo,
Daeyun Shim,
Chulwoo Kim,
Deog-Kyoon Jeong:
250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 μ m CMOS.
J. Solid-State Circuits 46(11): 2560-2570 (2011) |
| 2010 |
|---|
| 3 | | Young-Ho Kwak,
Inhwa Jung,
Chulwoo Kim:
A ħbox Gb/s+ Slew-Rate/Impedance-Controlled Output Driver With Single-Cycle Compensation Time.
IEEE Trans. on Circuits and Systems 57-II(2): 120-125 (2010) |
| 2009 |
|---|
| 2 | | Minyoung Song,
Young-Ho Kwak,
Sunghoon Ahn,
Wooseok Kim,
ByeongHa Park,
Chulwoo Kim:
A 10MHz to 315MHz cascaded hybrid PLL with piecewise linear calibrated TDC.
CICC 2009: 243-246 |
| 2008 |
|---|
| 1 | | Young-Ho Kwak,
Inhwa Jung,
Chulwoo Kim:
A slew-rate controlled output driver with one-cycle tuning time.
ASP-DAC 2008: 99-100 |
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