Ko-Chi Kuo

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2011

6 Ko-Chi Kuo, Chi-Wei Wu: A Switching Sequence for Linear Gradient Error Compensation in the DAC Design. IEEE Trans. on Circuits and Systems 58-II(8): 502-506 (2011)

2010

5 Ko-Chi Kuo, Chi-Wen Chou: Low power and high speed multiplier design with row bypassing and parallel architecture. Microelectronics Journal 41(10): 639-650 (2010)

2006

4 Ko-Chi Kuo, Feng-Ji Wu: A 2.4-GHz/5-GHz Low Power Pulse Swallow Counter in 0.18-µm CMOS Technology. APCCAS 2006: 214-217

3 Ko-Chi Kuo, Chi-Wen Chou: Low Power Multiplier with Bypassing and Tree Strucuture. APCCAS 2006: 602-605

2 Ko-Chi Kuo, Feng-Ji Wu: A CMOS High-Speed Nine-Stage Programmable Counter. IMECS 2006: 213-216

1 Ko-Chi Kuo, Chi-Wen Chou: A Low-Power Multiplier with Bypassing Logic and Operand Decomposition. IMECS 2006: 217-220

	2011
6		Ko-Chi Kuo, Chi-Wei Wu: A Switching Sequence for Linear Gradient Error Compensation in the DAC Design. IEEE Trans. on Circuits and Systems 58-II(8): 502-506 (2011)
	2010
5		Ko-Chi Kuo, Chi-Wen Chou: Low power and high speed multiplier design with row bypassing and parallel architecture. Microelectronics Journal 41(10): 639-650 (2010)
	2006
4		Ko-Chi Kuo, Feng-Ji Wu: A 2.4-GHz/5-GHz Low Power Pulse Swallow Counter in 0.18-µm CMOS Technology. APCCAS 2006: 214-217
3		Ko-Chi Kuo, Chi-Wen Chou: Low Power Multiplier with Bypassing and Tree Strucuture. APCCAS 2006: 602-605
2		Ko-Chi Kuo, Feng-Ji Wu: A CMOS High-Speed Nine-Stage Programmable Counter. IMECS 2006: 213-216
1		Ko-Chi Kuo, Chi-Wen Chou: A Low-Power Multiplier with Bypassing Logic and Operand Decomposition. IMECS 2006: 217-220

Coauthor Index

1 Chi-Wen Chou [1] [3] [5]

2 Chi-Wei Wu [6]

3 Feng-Ji Wu [2] [4]

Colors in the list of coauthors

Last update Fri Jun 1 15:44:53 2012 CET by the DBLP Team —

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