 | 2012 |
|---|
| 10 |       | Chia-Chun Tsai,
Chung-Chieh Kuo,
Feng-Tzu Hsu,
Trong-Yen Lee:
Discharge-path-based antenna effect detection and fixing for X-architecture clock tree.
Integration 45(1): 76-90 (2012) |
| 2011 |
|---|
| 9 | | Chia-Chun Tsai,
Chung-Chieh Kuo,
Trong-Yen Lee:
Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield Improvement.
IEICE Transactions 94-A(2): 706-716 (2011) |
| 8 | | Chung-Chieh Kuo,
Chia-Chun Tsai,
Trong-Yen Lee:
Pattern-matching-based X-architecture zero-skew clock tree construction with X-Flip technique and via delay consideration.
Integration 44(1): 87-101 (2011) |
| 2010 |
|---|
| 7 | | Chia-Chun Tsai,
Chung-Chieh Kuo,
Lin-Jeng Gu,
Trong-Yen Lee:
Double-via insertion enhanced X-architecture clock routing for reliability.
ISCAS 2010: 3413-3416 |
| 6 | | Chia-Chun Tsai,
Chung-Chieh Kuo,
Lin-Jeng Gu,
Trong-Yen Lee:
Antenna Violation Avoidance/Fixing for X-clock routing.
ISQED 2010: 508-514 |
| 2008 |
|---|
| 5 | | Chia-Chun Tsai,
Wei-Shi Lin,
Jan-Ou Wu,
Chung-Chieh Kuo,
Trong-Yen Lee:
Layer assignment considering manufacturability in X-architecture clock tree.
CIT 2008: 880-885 |
| 4 | | Chia-Chun Tsai,
Chung-Chieh Kuo,
Jan-Ou Wu,
Trong-Yen Lee,
Rong-Shue Hsiao:
X-clock routing based on pattern matching.
SoCC 2008: 357-360 |
| 2007 |
|---|
| 3 | | Jan-Ou Wu,
Chia-Chun Tsai,
Chung-Chieh Kuo,
Trong-Yen Lee:
Zero-Skew Driven Buffered RLC Clock Tree Construction.
IEICE Transactions 90-A(3): 651-658 (2007) |
| 2006 |
|---|
| 2 | | Chia-Chun Tsai,
Jan-Ou Wu,
Yu-Ting Shieh,
Chung-Chieh Kuo,
Trong-Yen Lee:
Tapping Point Numerical-Based Search for Exact Zero-Skew RLC Clock Tree Construction.
APCCAS 2006: 812-815 |
| 2005 |
|---|
| 1 | | Chia-Chun Tsai,
Jan-Ou Wu,
Chung-Chieh Kuo,
Trong-Yen Lee,
Wen-Ta Lee:
Zero-Skew Driven for RLC Clock Tree Construction in SoC.
ICITA (1) 2005: 561-566 |
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