 | 2012 |
|---|
| 9 |       | Chin-Cheng Kuo,
Wei-Yi Hu,
Yi-Hung Chen,
Jui-Feng Kuan,
Yi-Kan Cheng:
Efficient trimmed-sample Monte Carlo methodology and yield-aware design flow for analog circuits.
DAC 2012: 1113-1118 |
| 2010 |
|---|
| 8 | | Chin-Cheng Kuo,
Yen-Lung Chen,
I-Ching Tsai,
Li-Yu Chan,
Chien-Nan Jimmy Liu:
Behavior-level yield enhancement approach for large-scaled analog circuits.
DAC 2010: 903-908 |
| 7 | | Chin-Cheng Kuo,
Chien-Nan Jimmy Liu:
Fast and Accurate Analysis of Supply Noise Effects in PLL With Noise Interactions.
IEEE Trans. on Circuits and Systems 57-I(1): 44-52 (2010) |
| 2009 |
|---|
| 6 | | Chin-Cheng Kuo,
Pei-Syun Lin,
Chien-Nan Jimmy Liu:
A SCORE macromodel for PLL designs to analyze supply noise interaction issues at behavioral level.
ASP-DAC 2009: 516-521 |
| 5 | | Chin-Cheng Kuo,
Meng-Jung Lee,
Chien-Nan Jimmy Liu,
Ching-Ji Huang:
Fast Statistical Analysis of Process Variation Effects Using Accurate PLL Behavioral Models.
IEEE Trans. on Circuits and Systems 56-I(6): 1160-1172 (2009) |
| 4 | | Kuo-Hsing Cheng,
Yu-Chang Tsai,
Chien-Nan Jimmy Liu,
Kai-Wei Hong,
Chin-Cheng Kuo:
A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application.
IEICE Transactions 92-C(7): 964-972 (2009) |
| 2006 |
|---|
| 3 | | Chin-Cheng Kuo,
Chien-Nan Jimmy Liu:
On Efficient Behavioral Modeling to Accurately Predict Supply Noise Effects of PLL Designs in Real Systems.
VLSI-SoC 2006: 116-121 |
| 2 | | Chin-Cheng Kuo,
Yu-Chien Wang,
Chien-Nan Jimmy Liu:
An Efficient Approach to Build Accurate Behavioral Models of PLL Designs.
IEICE Transactions 89-A(2): 391-398 (2006) |
| 2005 |
|---|
| 1 | | Chin-Cheng Kuo,
Yu-Chien Wang,
Chien-Nan Jimmy Liu:
An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs.
ACM Great Lakes Symposium on VLSI 2005: 286-290 |
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