Wolfgang Kunz

	2012
48		Joakim Urdahl, Dominik Stoffel, Markus Wedler, Wolfgang Kunz: System verification of concurrent RTL modules by compositional path predicate abstraction. DAC 2012: 334-343
	2011
47		Minh D. Nguyen, Markus Wedler, Dominik Stoffel, Wolfgang Kunz: Formal hardware/software co-verification by interval property checking with abstraction. DAC 2011: 510-515
46		Evgeny Pavlenko, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Alexander Dreyer, Frank Seelisch, Gert-Martin Greuel: STABLE: A new QF-BV SMT solver for hard verification problems combining Boolean reasoning with computer algebra. DATE 2011: 155-160
45		Christian Brehm, Norbert Wehn, Sacha Loitz, Wolfgang Kunz: Validation of channel decoding ASIPs a case study. International Symposium on Rapid System Prototyping 2011: 74-78
	2010
44		Max Thalmaier, Minh D. Nguyen, Markus Wedler, Dominik Stoffel, Jörg Bormann, Wolfgang Kunz: Analyzing k-step induction to compute invariants for SAT-based property checking. DAC 2010: 176-181
43		Sacha Loitz, Markus Wedler, Dominik Stoffel, Christian Brehm, Norbert Wehn, Wolfgang Kunz: Complete Verification of Weakly Programmable IPs against Their Operational ISA Model. FDL 2010: 29-36
42		Joakim Urdahl, Dominik Stoffel, Jörg Bormann, Markus Wedler, Wolfgang Kunz: Path predicate abstraction by complete interval property checking. FMCAD 2010: 207-215
	2009
41		Minh D. Nguyen, Max Thalmaier, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Jörg Bormann: A re-use methodology for formal SoC protocol compliance verification. FDL 2009: 1-6
	2008
40		Udo Krautz, Markus Wedler, Wolfgang Kunz, Kai Weber, Christian Jacobi, Matthias Pflanz: Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof. ASP-DAC 2008: 398-403
39		Oliver Wienand, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Gert-Martin Greuel: An Algebraic Approach for Proving Data Correctness in Arithmetic Data Paths. CAV 2008: 473-486
38		Evgeny Pavlenko, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Oliver Wienand, Evgeny Karibaev: Modeling of Custom-Designed Arithmetic Components for ABL Normalization. FDL 2008: 124-129
37		Sacha Loitz, Markus Wedler, Christian Brehm, Timo Vogt, Norbert Wehn, Wolfgang Kunz: Proving Functional Correctness of Weakly Programmable IPs - A Case Study with Formal Property Checking. SASP 2008: 48-54
36		Minh D. Nguyen, Max Thalmaier, Markus Wedler, Jörg Bormann, Dominik Stoffel, Wolfgang Kunz: Unbounded Protocol Compliance Verification Using Interval Property Checking With Invariants. IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 2068-2082 (2008)
	2007
35		Markus Wedler, Dominik Stoffel, Raik Brinkmann, Wolfgang Kunz: A Normalization Method for Arithmetic Data-Path Verification. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 1909-1922 (2007)
	2005
34		Markus Wedler, Dominik Stoffel, Wolfgang Kunz: Normalization at the arithmetic bit level. DAC 2005: 457-462
33		Minh D. Nguyen, Dominik Stoffel, Wolfgang Kunz: Enhancing BMC-based Protocol Verification Using Transition-By-Transition FSM Traversal. GI Jahrestagung (1) 2005: 303-307
32		Minh D. Nguyen, Dominik Stoffel, Markus Wedler, Wolfgang Kunz: Transition-by-transition FSM traversal for reachability analysis in bounded model checking. ICCAD 2005: 1068-1075
	2004
31		Markus Wedler, Dominik Stoffel, Wolfgang Kunz: Exploiting state encoding for invariant generation in induction-based property checking. ASP-DAC 2004: 424-429
30		Markus Wedler, Dominik Stoffel, Wolfgang Kunz: Arithmetic Reasoning in DPLL-Based SAT Solving. DATE 2004: 30-35
29		Ingmar Neumann, Dominik Stoffel, Kolja Sulimma, Michel R. C. M. Berkelaar, Wolfgang Kunz: Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning. ICCD 2004: 350-353
28		Dominik Stoffel, Wolfgang Kunz: Equivalence checking of arithmetic circuits on the arithmetic bit level. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 586-597 (2004)
27		Dominik Stoffel, Markus Wedler, Peter Warkentin, Wolfgang Kunz: Structural FSM traversal. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 598-619 (2004)
	2003
26		Markus Wedler, Dominik Stoffel, Wolfgang Kunz: Using RTL Statespace Information and State Encoding for Induction Based Property Checking. DATE 2003: 11156-11157
25		Ingmar Neumann, Wolfgang Kunz: Layout driven retiming using the coupled edge timing model. IEEE Trans. on CAD of Integrated Circuits and Systems 22(7): 825-835 (2003)
	2002
24		Kolja Sulimma, Wolfgang Kunz, Ingmar Neumann, Lukas VanGinneken: Improving Placement under the Constant Delay Model. DATE 2002: 677-682
23		Armin Biere, Wolfgang Kunz: SAT and ATPG: Boolean engines for formal hardware verification. ICCAD 2002: 782-785
22		Ingmar Neumann, Kolja Sulimma, Wolfgang Kunz: Accelerating Retiming Under the Coupled-Edge Timing Model. ISVLSI 2002: 135-140
21		Markus Wedler, Dominik Stoffel, Wolfgang Kunz: Improving Structural FSM Traversal by Constraint-Satisfying Logic Simulation. ISVLSI 2002: 151-158
	2001
20		Dominik Stoffel, Wolfgang Kunz: Verification of Integer Multipliers on the Arithmetic Bit Level. ICCAD 2001: 183-189
19		Ingmar Neumann, Wolfgang Kunz: Placement Driven Retiming with a Coupled Edge Timing Model. ICCAD 2001: 95-102
18		Ingmar Neumann, Wolfgang Kunz: Tight coupling of timing-driven placement and retiming. ISCAS (5) 2001: 351-354
17		Hendrik Hartje, Ingmar Neumann, Dominik Stoffel, Wolfgang Kunz: Cycle time optimization by timing driven placement with simultaneous netlist transformations. ISCAS (5) 2001: 359-362
16		Kolja Sulimma, Wolfgang Kunz: An exact algorithm for solving difficult detailed routing problems. ISPD 2001: 198-203
15		Wolfgang Kunz, Dominik Stoffel: Äquivalenzvergleich mit strukturellen Methoden (Equivalence Checking using Structural Methods). it+ti - Informationstechnik und Technische Informatik 43(1): 8-15 (2001)
	1999
14		Kolja Sulimma, Dominik Stoffel, Wolfgang Kunz: Accelerating Boolean Implications with FPGAs. FPL 1999: 532-537
13		Ingmar Neumann, Dominik Stoffel, Hendrik Hartje, Wolfgang Kunz: Cell replication and redundancy elimination during placement for cycle time optimization. ICCAD 1999: 25-30
	1998
12		Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz: LOT: Logic Optimization with Testability. New transformations for logic synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 17(5): 386-399 (1998)
	1997
11		Dominik Stoffel, Wolfgang Kunz: Record & play: a structural fixed point iteration for sequential circuit verification. ICCAD 1997: 394-399
10		Wolfgang Kunz, Dominik Stoffel, Premachandran R. Menon: Logic optimization and equivalence checking by implication analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 266-281 (1997)
	1996
9		Dhiraj K. Pradhan, Mitrajit Chatterjee, Madhu V. Swarna, Wolfgang Kunz: Gate-level synthesis for low-power using new transformations. ISLPED 1996: 297-300
8		Wolfgang Kunz, Dhiraj K. Pradhan, Sudhakar M. Reddy: A novel framework for logic verification in a synthesis environment. IEEE Trans. on CAD of Integrated Circuits and Systems 15(1): 20-32 (1996)
	1995
7		Subodh M. Reddy, Wolfgang Kunz, Dhiraj K. Pradhan: Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment. DAC 1995: 414-419
6		Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz: LOT: logic optimization with testability-new transformations using recursive learning. ICCAD 1995: 318-325
	1994
5		Wolfgang Kunz, Premachandran R. Menon: Multi-level logic optimization by implication analysis. ICCAD 1994: 6-13
4		Wolfgang Kunz, Dhiraj K. Pradhan: Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 13(9): 1143-1158 (1994)
	1993
3		Wolfgang Kunz: HANNIBAL: an efficient tool for logic verification based on recursive learning. ICCAD 1993: 538-543
2		Wolfgang Kunz, Dhiraj K. Pradhan: Accelerated dynamic learning for test pattern generation in combinational circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 12(5): 684-694 (1993)
	1992
1		Wolfgang Kunz, Dhiraj K. Pradhan: Recursive Learning: An Attractive Alternative to the Decision Tree for Test Genration in Digital Circuits. ITC 1992: 816-825

Coauthor Index

1	Michel R. C. M. Berkelaar	[29]
2	Armin Biere	[23]
3	Jörg Bormann	[36] [41] [42] [44]
4	Christian Brehm	[37] [43] [45]
5	Raik Brinkmann	[35]
6	Mitrajit Chatterjee	[6] [9] [12]
7	Alexander Dreyer	[46]
8	Gert-Martin Greuel	[39] [46]
9	Hendrik Hartje	[13] [17]
10	Christian Jacobi	[40]
11	Evgeny Karibaev	[38]
12	Udo Krautz	[40]
13	Sacha Loitz	[37] [43] [45]
14	Premachandran R. Menon	[5] [10]
15	Ingmar Neumann	[13] [17] [18] [19] [22] [24] [25] [29]
16	Minh D. Nguyen	[32] [33] [36] [41] [44] [47]
17	Evgeny Pavlenko	[38] [46]
18	Matthias Pflanz	[40]
19	Dhiraj K. Pradhan	[1] [2] [4] [6] [7] [8] [9] [12]
20	Subodh M. Reddy	[7]
21	Sudhakar M. Reddy	[8]
22	Frank Seelisch	[46]
23	Dominik Stoffel	[10] [11] [13] [14] [15] [17] [20] [21] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [38] [39] [41] [42] [43] [44] [46] [47] [48]
24	Kolja Sulimma	[14] [16] [22] [24] [29]
25	Madhu V. Swarna	[9]
26	Max Thalmaier	[36] [41] [44]
27	Joakim Urdahl	[42] [48]
28	Lukas VanGinneken	[24]
29	Timo Vogt	[37]
30	Peter Warkentin	[27]
31	Kai Weber	[40]
32	Markus Wedler	[21] [26] [27] [30] [31] [32] [34] [35] [36] [37] [38] [39] [40] [41] [42] [43] [44] [46] [47] [48]
33	Norbert Wehn	[37] [43] [45]
34	Oliver Wienand	[38] [39]

Colors in the list of coauthors

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