 | 2011 |
|---|
| 8 |       | Yuji Kunitake,
Toshinori Sato,
Hiroto Yasuura:
Short Term Cell-Flipping Technique for Mitigating SNM Degradation Due to NBTI.
IEICE Transactions 94-C(4): 520-529 (2011) |
| 2010 |
|---|
| 7 | | Yuji Kunitake,
Toshinori Sato,
Hiroto Yasuura:
Signal probability control for relieving NBTI in SRAM cells.
ISQED 2010: 660-666 |
| 6 | | Yuji Kunitake,
Toshinori Sato,
Hiroto Yasuura:
A Replacement Strategy for Canary Flip-Flops.
PRDC 2010: 227-228 |
| 2009 |
|---|
| 5 | | Yuji Kunitake,
Kazuhiro Mima,
Toshinori Sato,
Hiroto Yasuura:
Enhancements of a Circuit-Level Timing Speculation Technique and Their Evaluations Using a Co-simulation Environment.
IEICE Transactions 92-C(4): 483-491 (2009) |
| 2008 |
|---|
| 4 | | Tohru Ishihara,
Seiichiro Yamaguchi,
Yuriko Ishitobi,
Tadayuki Matsumura,
Yuji Kunitake,
Yuichiro Oyama,
Yusuke Kaneda,
Masanori Muroyama,
Toshinori Sato:
AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications.
SASP 2008: 83-88 |
| 2007 |
|---|
| 3 | | Yuji Kunitake,
Akihiro Chiyonobu,
Koichiro Tanaka,
Toshinori Sato:
Challenges in Evaluations for a Typical-Case Design Methodology.
ISQED 2007: 374-379 |
| 2 | | Toshinori Sato,
Yuji Kunitake:
A Simple Flip-Flop Circuit for Typical-Case Designs for DFM.
ISQED 2007: 539-544 |
| 1 | | Toshinori Sato,
Yuji Kunitake:
Exploiting Input Variations for Energy Reduction.
PATMOS 2007: 384-393 |
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