Hiroyuki Kunishima

	2007
2		Noriaki Oda, Hironori Imura, Naoyoshi Kawahara, Masayoshi Tagami, Hiroyuki Kunishima, Shuji Sone, Sadayuki Ohnishi, Kenta Yamada, Yumi Kakuhara, Makoto Sekine, Yoshihiro Hayashi, Kazuyoshi Ueno: Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation. IEICE Transactions 90-C(4): 848-855 (2007)
	2006
1		Noriaki Oda, Hiroyuki Kunishima, Takashi Kyouno, Kazuhiro Takeda, Tomoaki Tanaka, Toshiyuki Takewaki, Masahiro Ikeda: Chip-Level Performance Improvement Using Triple Damascene Wiring Design Concept for the 0.13 µm CMOS Generation and Beyond. IEICE Transactions 89-C(11): 1544-1550 (2006)

Coauthor Index

1	Yoshihiro Hayashi	[2]
2	Masahiro Ikeda	[1]
3	Hironori Imura	[2]
4	Yumi Kakuhara	[2]
5	Naoyoshi Kawahara	[2]
6	Takashi Kyouno	[1]
7	Noriaki Oda	[1] [2]
8	Sadayuki Ohnishi	[2]
9	Makoto Sekine	[2]
10	Shuji Sone	[2]
11	Masayoshi Tagami	[2]
12	Kazuhiro Takeda	[1]
13	Toshiyuki Takewaki	[1]
14	Tomoaki Tanaka	[1]
15	Kazuyoshi Ueno	[2]
16	Kenta Yamada	[2]

Last update Fri Jun 1 15:44:53 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page