Shigeo Kuninobu

	1997
3		Toshinori Hosokawa, Toshihiro Hiraoka, Mitsuyasu Ohta, Michiaki Muraoka, Shigeo Kuninobu: A Partial Scan Design Method Based on n-Fold Line-up Structures. Asian Test Symposium 1997: 306-
	1994
2		Hideyuki Kabuo, Takashi Taniguchi, Akira Miyoshi, Hitoshi Yamashita, Miki Urano, Hisakazu Edamatsu, Shigeo Kuninobu: Accurate Ronding Scheme for the Newton-Raphson Method Using Redundant Binary Representation. IEEE Trans. Computers 43(1): 43-51 (1994)
	1987
1		Shigeo Kuninobu, Tamotsu Nishiyama, Hisakazu Edamatsu, Takashi Taniguchi, Naofumi Takagi: Design of high speed MOS multiplier and divider using redundant binary representation. IEEE Symposium on Computer Arithmetic 1987: 80-86

Coauthor Index

1	Hisakazu Edamatsu	[1] [2]
2	Toshihiro Hiraoka	[3]
3	Toshinori Hosokawa	[3]
4	Hideyuki Kabuo	[2]
5	Akira Miyoshi	[2]
6	Michiaki Muraoka	[3]
7	Tamotsu Nishiyama	[1]
8	Mitsuyasu Ohta	[3]
9	Naofumi Takagi	[1]
10	Takashi Taniguchi	[1] [2]
11	Miki Urano	[2]
12	Hitoshi Yamashita	[2]

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