Paul D. Kundarewich

	2009
4		Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson: Packing Techniques for Virtex-5 FPGAs. TRETS 2(3): (2009)
	2008
3		Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson, Brad L. Taylor, Rajat Aggarwal: Architecture-specific packing for virtex-5 FPGAs. FPGA 2008: 5-13
	2004
2		Paul D. Kundarewich, Jonathan Rose: Synthetic circuit generation using clustering and iteration. IEEE Trans. on CAD of Integrated Circuits and Systems 23(6): 869-887 (2004)
	2003
1		Paul D. Kundarewich, Jonathan Rose: Synthetic circuit generation using clustering and iteration. FPGA 2003: 245

Coauthor Index

1	Rajat Aggarwal	[3]
2	Taneem Ahmed	[3] [4]
3	Jason Helge Anderson	[3] [4]
4	Jonathan Rose	[1] [2]
5	Brad L. Taylor	[3]

Last update Fri Jun 1 15:44:53 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page