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| 2012 | ||
|---|---|---|
| 12 | Hironori Sakamoto, Shigetaka Kumashiro, Shigeo Sato, Naoki Wakita, Tohru Mogami: HiSIM-RP: A reverse-profiling based 1st principles compact MOSFET model and its application to variability analysis of 90nm and 40nm CMOS. ISQED 2012: 553-560 | |
| 11 | Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata: On-Chip In-Place Measurements of Vth and Signal/Substrate Response of Differential Pair Transistors. IEICE Transactions 95-C(1): 137-145 (2012) | |
| 2011 | ||
| 10 | Satoshi Takaya, Yoji Bando, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata: Accurate analysis of substrate sensitivity of active transistors in an analog circuit. ISQED 2011: 56-61 | |
| 9 | Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata: A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits. IEICE Transactions 94-C(4): 495-503 (2011) | |
| 8 | Masaaki Souda, Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata: On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement. IEICE Transactions 94-C(6): 1024-1031 (2011) | |
| 2010 | ||
| 7 | Kenta Yamada, Toshiyuki Syo, Hisao Yoshimura, Masaru Ito, Tatsuya Kunikiyo, Toshiki Kanamoto, Shigetaka Kumashiro: Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns. IEICE Transactions 93-C(8): 1349-1358 (2010) | |
| 2008 | ||
| 6 | Kenta Yamada, Takashi Sato, Shuhei Amakawa, Noriaki Nakayama, Kazuya Masu, Shigetaka Kumashiro: Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress. IEICE Transactions 91-C(7): 1142-1150 (2008) | |
| 5 | Tatsuya Ezaki, Dondee Navarro, Youichi Takeda, Norio Sadachika, G. Suzuki, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Tatsuya Ohguro, Takahiro Iizuka, Masahiko Taguchi, Shigetaka Kumashiro, Shunsuke Miyamoto: Non-quasi-static approach with surface-potential-based MOSFET model HiSIM for RF circuit simulations. Mathematics and Computers in Simulation 79(4): 1096-1106 (2008) | |
| 2005 | ||
| 4 | Shizunori Matsumoto, Hiroaki Ueno, Satoshi Hosokawa, Toshihiko Kitamura, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Tatsuya Ohguro, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama: 1/f-Noise Characteristics in 100 nm-MOSFETs and Its Modeling for Circuit Simulation. IEICE Transactions 88-C(2): 247-254 (2005) | |
| 3 | Dondee Navarro, Takeshi Mizoguchi, Masami Suetake, Kazuya Hisamitsu, Hiroaki Ueno, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama: A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential. IEICE Transactions 88-C(5): 1079-1086 (2005) | |
| 2001 | ||
| 2 | D. Miyawaki, Shizunori Matsumoto, Hans Jürgen Mattausch, S. Ooshiro, Masami Suetake, Michiko Miura-Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama: Correlation method of circuit-performance and technology fluctuations for improved design reliability. ASP-DAC 2001: 39-44 | |
| 1993 | ||
| 1 | Shigetaka Kumashiro, Ronald A. Rohrer, Andrzej J. Strojwas: Asymptotic waveform evaluation for transient analysis of 3-D interconnect structures. IEEE Trans. on CAD of Integrated Circuits and Systems 12(7): 988-996 (1993) | |
Colors in the list of coauthors
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