 | 2011 |
|---|
| 11 |       | Jiun-Ping Wang,
Shiann-Rong Kuang,
Shish-Chang Liang:
High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications.
IEEE Trans. VLSI Syst. 19(1): 52-60 (2011) |
| 2010 |
|---|
| 10 | | Shiann-Rong Kuang,
Jiun-Ping Wang,
Hong-Yi Huang:
Variable-Latency Floating-Point Multipliers for Low-Power Applications.
IEEE Trans. VLSI Syst. 18(10): 1493-1497 (2010) |
| 9 | | Shiann-Rong Kuang,
Jiun-Ping Wang:
Design of Power-Efficient Configurable Booth Multiplier.
IEEE Trans. on Circuits and Systems 57-I(3): 568-580 (2010) |
| 2009 |
|---|
| 8 | | Shiann-Rong Kuang,
Jiun-Ping Wang,
Cang-Yuan Guo:
Modified Booth Multipliers With a Regular Partial Product Array.
IEEE Trans. on Circuits and Systems 56-II(5): 404-408 (2009) |
| 2007 |
|---|
| 7 | | Jiun-Ping Wang,
Shiann-Rong Kuang:
Area-Efficient Signed Fixed-Width Multipliers with Low-Error Compensation Circuit.
SiPS 2007: 157-162 |
| 6 | | Shiann-Rong Kuang,
Jiun-Ping Wang:
Design of power-efficient pipelined truncated multipliers with various output precision.
IET Computers & Digital Techniques 1(2): 129-136 (2007) |
| 2005 |
|---|
| 5 | | Shiann-Rong Kuang,
Chin-Yang Chen,
Ren-Zheng Liao:
Partitioning and Pipelined Scheduling of Embedded System Using Integer Linear Programming.
ICPADS (2) 2005: 37-41 |
| 2002 |
|---|
| 4 | | Jer-Min Jou,
Shiann-Rong Kuang,
Yeu-Horng Shiau,
Ren-Der Chen:
Design of a dynamic pipelined architecture for fuzzy color correction.
IEEE Trans. VLSI Syst. 10(6): 924-929 (2002) |
| 1999 |
|---|
| 3 | | Jer-Min Jou,
Shiann-Rong Kuang,
Yeu-Horng Shiau:
A New Pipelined Architecture for Fuzzy Color Correction.
ASP-DAC 1999: 209- |
| 1994 |
|---|
| 2 |  | Jer-Min Jou,
Ren-Der Chen,
Shiann-Rong Kuang:
Multiport Memory Based Data Path Allocation Focusing on Interconnection Optimization.
ISCAS 1994: 45-48 |
| 1993 |
|---|
| 1 | | Jer-Min Jou,
Shiann-Rong Kuang:
Library-Adaptively Integrated Data Path Synthesis for DSP Systems.
ICCD 1993: 379-382 |
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