 | 2011 |
|---|
| 8 |       | Chia-Yu Lin,
Chih-Chun Wei,
Mong-Kai Ku:
Two-Way Parity Bit Correction Encoding Algorithm for Dual-Diagonal LDPC Codes.
IEICE Transactions 94-A(2): 773-780 (2011) |
| 2009 |
|---|
| 7 | | Chia-Yu Lin,
Mong-Kai Ku:
Node Operation Reduced Decoding for LDPC Codes.
ISCAS 2009: 896-899 |
| 6 | | Chun F. Hsu,
Mong-Kai Ku,
Li-Yen Liu:
Support vector machine FPGA implementation for video shot boundary detection application.
SoCC 2009: 239-242 |
| 2008 |
|---|
| 5 | | Shu-Cheng Chou,
Mong-Kai Ku,
Chia-Yu Lin:
Switching activity reducing layered decoding algorithm for LDPC codes.
ISCAS 2008: 528-531 |
| 4 | | Chia-Yu Lin,
Mong-Kai Ku,
Yi-Hsing Chien:
Long Length LDPC Code Construction and the Corresponding Decoder Implementation with Adjustable Parallelism.
VTC Spring 2008: 1423-1427 |
| 2007 |
|---|
| 3 | | Shao-Yi Chien,
Chi-Sheng Shih,
Mong-Kai Ku,
Chia-Lin Yang,
Yao-Wen Chang,
Tei-Wei Kuo,
Liang-Gee Chen:
3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design.
ICME 2007: 9 |
| 2 | | Yi-Hsing Chien,
Mong-Kai Ku:
A High Throughput H-QC LDPC Decoder.
ISCAS 2007: 1649-1652 |
| 2005 |
|---|
| 1 | | Chi-Sheng Shih,
Chia-Lin Yang,
Mong-Kai Ku,
Tei-Wei Kuo,
Shao-Yi Chien,
Yao-Wen Chang,
Liang-Gee Chen:
Reconfigurable Platform for Content Science Research.
RTCSA 2005: 481-486 |
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