Narayanan Krishnamurthy

	2005
12		Prabhat Mishra, Nikil D. Dutt, Narayanan Krishnamurthy, Magdy S. Abadir: A methodology for validation of microprocessors using symbolic simulation. IJES 1(1/2): 14-22 (2005)
	2004
11		Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham: Towards The Complete Elimination of Gate/Switch Level Simulations. VLSI Design 2004: 115-
10		Prabhat Mishra, Nikil Dutt, Narayanan Krishnamurthy, Magdy S. Abadir: A Top-Down Methodology for Microprocessor Validation. IEEE Design & Test of Computers 21(2): 122-131 (2004)
9		Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir: Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation. IEEE Design & Test of Computers 21(6): 494-502 (2004)
	2003
8		Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir: A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits. MTV 2003: 32-37
7		Magdy S. Abadir, Ken Albin, John Havlicek, Narayanan Krishnamurthy, Andrew K. Martin: Formal Verification Successes at Motorola. Formal Methods in System Design 22(2): 117-123 (2003)
	2002
6		Jayanta Bhadra, Narayanan Krishnamurthy: Automatic Generation of Design Constraints in Verifying High Performance Embedded Dynamic Circuits. ITC 2002: 213-222
5		Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham: Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? VTS 2002: 275-280
	2001
4		Narayanan Krishnamurthy, Magdy S. Abadir, Andrew K. Martin, Jacob A. Abraham: Design and Development Paradigm for Industrial Formal Verification CAD Tools. IEEE Design & Test of Computers 18(4): 26-35 (2001)
	2000
3		Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham: Validation of PowerPC(tm) Custom Memories using Symbolic Simulation. VTS 2000: 9-14
2		Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham: Validating PowerPC Microprocessor Custom Memories. IEEE Design & Test of Computers 17(4): 61-76 (2000)
	1999
1		Zeyad Alkhalifa, V. S. S. Nair, Narayanan Krishnamurthy, Jacob A. Abraham: Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection. IEEE Trans. Parallel Distrib. Syst. 10(6): 627-641 (1999)

Coauthor Index

1	Magdy S. Abadir	[2] [3] [4] [5] [7] [8] [9] [10] [11] [12]
2	Jacob A. Abraham	[1] [2] [3] [4] [5] [11]
3	Ken Albin	[7]
4	Zeyad Alkhalifa	[1]
5	Jayanta Bhadra (Jay Bhadra)	[5] [6] [8] [9] [11]
6	Nikil D. Dutt (Nikil Dutt)	[10] [12]
7	John Havlicek	[7]
8	Andrew K. Martin	[2] [3] [4] [7]
9	Prabhat Mishra	[10] [12]
10	Suku Nair (V. S. S. Nair)	[1]

Last update Sat Jun 2 20:57:36 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page