 | 2011 |
| 10 |  | Alan Mishchenko,
Robert K. Brayton,
Stephen Jang,
Victor N. Kravets:
Delay optimization using SOP balancing.
ICCAD 2011: 375-382 |
| 2009 |
| 9 |  | Victor N. Kravets,
Alan Mishchenko:
Sequential logic synthesis using symbolic bi-decomposition.
DATE 2009: 1458-1463 |
| 8 |  | Haoxing Ren,
Mary P. Kusko,
Victor N. Kravets,
Rona Yaari:
Low cost test point insertion without using extra registers for high performance design.
ITC 2009: 1-8 |
| 2008 |
| 7 |  | Michael L. Case,
Victor N. Kravets,
Alan Mishchenko,
Robert K. Brayton:
Merging nodes under sequential observability.
DAC 2008: 540-545 |
| 2004 |
| 6 |  | Victor N. Kravets,
Prabhakar Kudva:
Implicit enumeration of structural changes in circuit optimization.
DAC 2004: 438-441 |
| 2003 |
| 5 |  | Victor N. Kravets,
Prabhakar Kudva:
Understanding metrics in logic synthesis for routability enhancement.
SLIP 2003: 3-5 |
| 2002 |
| 4 |  | Victor N. Kravets,
Karem A. Sakallah:
Resynthesis of multi-level circuits under tight constraints using symbolic optimization.
ICCAD 2002: 687-693 |
| 2000 |
| 3 |  | Victor N. Kravets,
Karem A. Sakallah:
Constructive Library-Aware Synthesis Using Symmetries.
DATE 2000: 208-213 |
| 2 |  | Victor N. Kravets,
Karem A. Sakallah:
Generalized Symmetries in Boolean Functions.
ICCAD 2000: 526-532 |
| 1998 |
| 1 |  | Victor N. Kravets,
Karem A. Sakallah:
M32: A Constructive multilevel Logic Synthesis System.
DAC 1998: 336-341 |