Yana Esteves Krasteva

	2010
9		Andrés Otero, Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo: Generic Systolic Array for Run-Time Scalable Cores. ARC 2010: 4-16
8		Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Yana Esteves Krasteva: Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs. FPL 2010: 70-76
7		Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo: Reconfigurable Networks on Chip: DRNoC architecture. Journal of Systems Architecture - Embedded Systems Design 56(7): 293-302 (2010)
	2008
6		Yana Esteves Krasteva, Francisco Criado, Eduardo de la Torre, Teresa Riesgo: A Fast Emulation-Based NoC Prototyping Framework. ReConFig 2008: 211-216
	2007
5		Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo: Reconfigurable Heterogeneous Communications and Core Reallocation for Dynamic HW Task Management. ISCAS 2007: 873-876
	2006
4		Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo, Didier Joly: Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems. FPL 2006: 1-4
3		Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo: Partial Reconfiguration for Core Reallocation and Flexible Communications. ReCoSoC 2006: 91-97
	2005
2		Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo: Flexible Core Reallocation for Virtex II Structures. ERSA 2005: 189-195
1		Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo: Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs. IEEE International Workshop on Rapid System Prototyping 2005: 77-83

Coauthor Index

1	Francisco Criado	[6]
2	Ana B. Jimeno	[1] [2]
3	Didier Joly	[4]
4	Andrés Otero	[8] [9]
5	Teresa Riesgo	[1] [2] [3] [4] [5] [6] [7] [8] [9]
6	Eduardo de la Torre	[1] [2] [3] [4] [5] [6] [7] [8] [9]

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