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| 2012 | ||
|---|---|---|
| 23 | Noboru Shibata, Kazushige Kanda, T. Hisada, Katsuaki Isobe, M. Sato, Y. Shimizu, Takahiro Shimizu, T. Sugimoto, T. Kobayashi, K. Inuzuka, Naoaki Kanagawa, Yasuyuki Kajitani, Takeshi Ogawa, J. Nakai, Kiyoaki Iwasa, M. Kojima, Toshihiro Suzuki, Y. Suzuki, S. Sakai, Tomofumi Fujimura, Y. Utsunomiya, Toshifumi Hashimoto, M. Miakashi, N. Kobayashi, M. Inagaki, Y. Matsumoto, S. Inoue, Y. Suzuki, D. He, Y. Honda, Junji Musha, M. Nakagawa, Mitsuaki Honma, Naofumi Abiko, Mitsumasa Koyanagi, M. Yoshihara, Kazumi Ino, Mitsuhiro Noguchi, Teruhiko Kamei, Yosuke Kato, S. Zaitsu, Hiroaki Nasu, T. Ariki, Hardwell Chibvongodze, Mitsuyuki Watanabe, H. Ding, N. Ookuma, R. Yamashita, G. Liang, Gertjan Hemink, Farookh Moogat, Cuong Trinh, Masaaki Higashitani, Tuan Pham, K. Kanazawa: A 19nm 112.8mm2 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface. ISSCC 2012: 422-424 | |
| 2011 | ||
| 22 | Mitsumasa Koyanagi: 3D super chip technology to achieve low-power and high-performance system-on-a chip. ISLPED 2011: 61-62 | |
| 21 | Takafumi Fukushima, Takayuki Konno, Eiji Iwata, Risato Kobayashi, Toshiya Kojima, Mariappan Murugesan, Ji Chel Bea, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi: Self-Assembly of Chip-Size Components with Cavity Structures: High-Precision Alignment and Direct Bonding without Thermal Compression for Hetero Integration. Micromachines 2(1): 49-68 (2011) | |
| 2010 | ||
| 20 | Kouji Kiyoyama, Kang Wook Lee, Takafumi Fukushima, H. Naganuma, Hiroaki Kobayashi, Tetsu Tanaka, Mitsumasa Koyanagi: A block-parallel signal processing system for CMOS image sensor with three-dimensional structure. 3DIC 2010: 1-4 | |
| 19 | Akihiro Noriki, Kang Wook Lee, Jichoel Bea, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi: Through Silicon photonic via (TSPV) with Si core for low loss and high-speed data transmission in opto-electronic 3-D LSI. 3DIC 2010: 1-4 | |
| 18 | Takafumi Fukushima, Eiji Iwata, Jichoel Bea, Mariappan Murugesan, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi: Evaluation of alignment accuracy on chip-to-wafer self-assembly and mechanism on the direct chip bonding at room temperature. 3DIC 2010: 1-5 | |
| 17 | Mariappan Murugesan, Yuki Ohara, Jichoel Bea, Kang Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi: Impact of microbump induced stress in thinned 3D-LSIs after wafer bonding. 3DIC 2010: 1-5 | |
| 16 | Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka: Three-dimensional integration technology using through-si via based on reconfigured wafer-to-wafer bonding. CICC 2010: 1-4 | |
| 2009 | ||
| 15 | Yoshiyuki Kaiho, Yuki Ohara, Hirotaka Takeshita, Kouji Kiyoyama, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi: 3D integration technology for 3D stacked retinal chip. 3DIC 2009: 1-4 | |
| 14 | Kouji Kiyoyama, Yuki Ohara, Kang Wook Lee, Y. Yang, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi: A parallel ADC for high-speed CMOS image processing system with 3D structure. 3DIC 2009: 1-4 | |
| 13 | Takafumi Fukushima, Eiji Iwata, Tetsu Tanaka, Mitsumasa Koyanagi: Development of a new self-assembled die bonder to three-dimensionally stack known good dies in batch. 3DIC 2009: 1-4 | |
| 12 | Ji Chel Bea, Mariappan Murugesan, Yuki Ohara, Akihiro Noriki, Hisaski Kino, Kang Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi: Micro-Raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration. 3DIC 2009: 1-5 | |
| 11 | Yuki Ohara, Akihiro Noriki, Katsuyuki Sakuma, Kang Wook Lee, Mariappan Murugesan, Jichoel Bea, Fumiaki Yamada, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi: 10 µm fine pitch Cu/Sn micro-bumps for 3-D super-chip stack. 3DIC 2009: 1-6 | |
| 10 | Kang Wook Lee, Shigeyuki Kanno, Yuki Ohara, Kouji Kiyoyama, Ji Chel Bea, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi: Heterogeneous integration technology for MEMS-LSI multi-chip module. 3DIC 2009: 1-6 | |
| 9 | Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka: Three-dimensional integration technology and integrated systems. ASP-DAC 2009: 409-415 | |
| 2006 | ||
| 8 | Atsushi Konno, Ryo Uchikura, Toshiyuki Ishihara, Teppei Tsujita, Takeaki Sugimura, Jun Deguchi, Mitsumasa Koyanagi, Masaru Uchiyama: Development of a High Speed Vision System for Mobile Robots. IROS 2006: 1372-1377 | |
| 2005 | ||
| 7 | Takeaki Sugimura, Yuta Konishi, Yoshihiro Nakatani, Takafumi Fukushima, Hiroyuki Kurino, Mitsumasa Koyanagi: Dynamic Multi-Context Reconfiguration Scheme for Reconfigurable Parallel Image Processing System with Three Dimensional Structure. ARCS Workshops 2005: 27-32 | |
| 2004 | ||
| 6 | Zhe Liu, JeoungChill Shim, Hiroyuki Kurino, Mitsumasa Koyanagi: Design of A Novel Real-Shared Memory Module for High Performance Parallel Processor System with Shared Memory. AINA (2) 2004: 241-244 | |
| 5 | Zhe Liu, JeoungChill Shim, Hiroyuki Kurino, Mitsumasa Koyanagi: Design and Evaluation of a Novel Real-Shared Cache Module for High Performance Parallel Processor Chip. PDCAT 2004: 564-569 | |
| 2002 | ||
| 4 | Robert W. Brodersen, Anthony M. Hill, John Kibarian, Desmond Kirkpatrick, Mark A. Lavin, Mitsumasa Koyanagi: Nanometer design: what hurts next...? DAC 2002: 242 | |
| 2000 | ||
| 3 | Hiroyuki Kurino, M. Nakagawa, Kang Wook Lee, Tomonori Nakamura, Yuusuke Yamada, Ki Tae Park, Mitsumasa Koyanagi: Smart Vision Chip Fabricated Using Three Dimensional Integration Technology. NIPS 2000: 720-726 | |
| 1998 | ||
| 2 | K. Hirano, T. Ono, Hiroyuki Kurino, Mitsumasa Koyanagi: A New Multiport Memory for High Performance Parallel Processor System with Shared Memory. ASP-DAC 1998: 333-334 | |
| 1991 | ||
| 1 | Mitsumasa Koyanagi: A New Chip Architecture for VLSIs - Optical Coupled 3D Common Memory and Optical Interconnections. VLSI 1991: 377-386 | |
Colors in the list of coauthors
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