Saurabh Kotiyal

	2012
4		Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan: Mach-Zehnder interferometer based design of all optical reversible binary adder. DATE 2012: 721-726
	2006
3		Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas: Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format. VLSI Design 2006: 387-392
2		Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas: Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format CoRR abs/cs/0603088: (2006)
	2005
1		Saurabh Kotiyal, Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia: VLSI Implementation of O(n*n) Sorting Algorithms And Their Hardware Comparison. CSC 2005: 74-77

Coauthor Index

1	Hamid R. Arabnia	[1]
2	N. Ranganathan (Nagarajan Ranganathan)	[4]
3	M. B. Srinivas (Mandalika B. Srinivas)	[1] [2] [3]
4	Himanshu Thapliyal	[1] [2] [3] [4]

Last update Sun Jun 3 16:06:10 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page