George Kornaros

	2011
25		George Kornaros, Dionisios N. Pnevmatikatos: Hardware-assisted dynamic power and thermal management in multi-core SoCs. ACM Great Lakes Symposium on VLSI 2011: 115-120
24		Antonios Motakis, George Kornaros, Marcello Coppola: Dynamic resource management in modern multicore SoCs by exposing NoC services. ReCoSoC 2011: 1-7
23		Miltos D. Grammatikakis, George Kornaros, Marcello Coppola: Power-Aware Multicore SoC and NoC Design. Multiprocessor System-on-Chip 2011: 167-193
	2010
22		George Kornaros, Antonios Motakis: On Scaling Speedup with Coarse-Grain Coprocessor Accelerators on Reconfigurable Platforms. DSD 2010: 355-362
21		George Kornaros: NCXplore: a design space exploration framework of temporal encoding for on-chip serial interconnects. IJHPSA 2(3/4): 177-186 (2010)
20		George Kornaros: A soft multi-core architecture for edge detection and data analysis of microarray images. Journal of Systems Architecture - Embedded Systems Design 56(1): 48-62 (2010)
19		George Kornaros, Theofanis Orphanoudakis: Design and implementation of high-speed buffered crossbars with efficient load balancing for multi-core SoCs. Microprocessors and Microsystems - Embedded Hardware Design 34(7-8): 301-315 (2010)
	2008
18		George Kornaros, Wolfram Lautenschlaeger, Matthias Sund, Helen-Catherine Leligou: Architecture and implementation of a Frame Aggregation Unit for optical frame-based switching. FPL 2008: 639-642
17		George Kornaros, Spyros Blionas: Microarchitecture of a MultiCore SoC for Data Analysis of a Lab-on-Chip Microarray. EURASIP J. Adv. Sig. Proc. 2008: (2008)
	2007
16		Ioannis Papaefstathiou, George Kornaros, Nikolaos Chrysos: A buffered crossbar-based chip interconnection framework supporting quality of service. ACM Great Lakes Symposium on VLSI 2007: 90-95
15		Theofanis Orphanoudakis, George Kornaros, Ioannis Mavroidis, Aristides Nikologiannis, Ioannis Papaefstathiou: An Embedded Networking SoC for purely Ethernet MANs/WANs. ISCC 2007: 901-906
14		Ioannis Papaefstathiou, Theofanis Orphanoudakis, George Kornaros, Christopher Kachris, Ioannis Mavroidis, Aristides Nikologiannis: Queue Management in Network Processors CoRR abs/0710.4813: (2007)
	2006
13		George Kornaros: BCB: A Buffered CrossBar Switch Fabric Utilizing Shared Memory. DSD 2006: 180-188
	2005
12		Ioannis Papaefstathiou, Theofanis Orphanoudakis, George Kornaros, Christopher Kachris, Ioannis Mavroidis, Aristides Nikologiannis: Queue Management in Network Processors. DATE 2005: 112-117
	2004
11		Ioannis Papaefstathiou, George Kornaros, Nicholaos Zervos: Software Processing Performance in Network Processors. DATE 2004: 186-191
10		Ioannis Papaefstathiou, Stylianos Perissakis, Theofanis Orphanoudakis, Nikos A. Nikolaou, George Kornaros, Nicholas Zervos, George E. Konstantoulakis, Dionisios N. Pnevmatikatos, Kyriakos Vlachos: PRO3: A Hybrid NPU Architecture. IEEE Micro 24(5): 20-33 (2004)
9		Aristides Nikologiannis, Ioannis Papaefstathiou, George Kornaros, Christopher Kachris: An FPGA-based queue management system for high speed networking devices. Microprocessors and Microsystems 28(5-6): 223-236 (2004)
	2003
8		George Kornaros, Theofanis Orphanoudakis, Ioannis Papaefstathiou: GFS: An Efficient Implementation of Fair Scheduling for Mult-Gigabit Packet Networks. ASAP 2003: 389-399
7		George Kornaros, Ioannis Papaefstathiou, Aristides Nikologiannis, Nicholaos Zervos: A fully-programmable memory management system optimizing queue handling at multi-gigabit rates. DAC 2003: 54-59
6		George Kornaros, Theofanis Orphanoudakis, Nicholaos Zervos: An Efficient Implementation of Fair Load Balancing over Multi-CPU SOC Architectures. DSD 2003: 197-205
5		George Kornaros, Ioannis Papaefstathiou: An Innovative Resource Management Scheme for Multi-gigabit Networking Systems. HSNMC 2003: 165-175
4		Ioannis Papaefstathiou, Helen-Catherine Leligou, Theofanis Orphanoudakis, George Kornaros, Nicholaos Zervos, George E. Konstantoulakis: An innovative scheduling scheme for high-speed network processors. ISCAS (2) 2003: 93-96
3		George Kornaros, Theofanis Orphanoudakis, Ioannis Papaefstathiou: Active flow identifiers for scalable, QoS scheduling in 10-Gbps network processors. ISCAS (2) 2003: 97-100
2		Kyriakos Vlachos, Nikos A. Nikolaou, Theofanis Orphanoudakis, Stylianos Perissakis, Dionisios N. Pnevmatikatos, George Kornaros, J. A. Sanchez, George E. Konstantoulakis: Processing and Scheduling Components in an Innovative Network Processor Architecture. VLSI Design 2003: 195-201
	1997
1		George Kornaros, Christoforos E. Kozyrakis, Panagiota Vatsolaki, Manolis Katevenis: Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control. ARVLSI 1997: 127-144

Coauthor Index

1	Spyros Blionas	[17]
2	Nikolaos Chrysos	[16]
3	Marcello Coppola	[23] [24]
4	Miltos D. Grammatikakis	[23]
5	Christoforos Kachris (Christopher Kachris)	[9] [12] [14]
6	Manolis Katevenis	[1]
7	George E. Konstantoulakis	[2] [4] [10]
8	Christoforos E. Kozyrakis (Christos Kozyrakis)	[1]
9	Wolfram Lautenschlaeger	[18]
10	Helen-Catherine Leligou	[4] [18]
11	Ioannis Mavroidis	[12] [14] [15]
12	Antonios Motakis	[22] [24]
13	Nikos A. Nikolaou	[2] [10]
14	Aristides Nikologiannis	[7] [9] [12] [14] [15]
15	Theofanis Orphanoudakis	[2] [3] [4] [6] [8] [10] [12] [14] [15] [19]
16	Ioannis Papaefstathiou	[3] [4] [5] [7] [8] [9] [10] [11] [12] [14] [15] [16]
17	Stylianos Perissakis	[2] [10]
18	Dionisios N. Pnevmatikatos	[2] [10] [25]
19	J. A. Sanchez	[2]
20	Matthias Sund	[18]
21	Panagiota Vatsolaki	[1]
22	Kyriakos Vlachos	[2] [10]
23	Nicholaos Zervos (Nicholas Zervos)	[4] [6] [7] [10] [11]

Colors in the list of coauthors

Last update Sun Jun 3 16:06:10 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page