 | 2011 |
|---|
| 8 |       | Tomoyuki Nakabayashi,
Takahiro Sasaki,
Kazuhiko Ohno,
Toshio Kondo:
Design and evaluation of variable stages pipeline processor chip.
ASP-DAC 2011: 95-96 |
| 2010 |
|---|
| 7 | | Tomoyuki Nakabayashi,
Takahiro Sasaki,
Kazuhiko Ohno,
Toshio Kondo:
Design and Evaluation of Variable Stages Pipeline Processor Chip.
ISIA 2010: 220-226 |
| 6 | | Nobuyuki Matsubara,
Takahiro Sasaki,
Kazuhiko Ohno,
Toshio Kondo:
Evaluation of Variable Level Cache.
ISIA 2010: 227-233 |
| 2008 |
|---|
| 5 | | Takahiro Sasaki,
Yuji Ichikawa,
Tetsuo Hironaka,
Toshiaki Kitamura,
Toshio Kondo:
Evaluation of low-energy and high-performance processor using variable stages pipeline technique.
IET Computers & Digital Techniques 2(3): 230-238 (2008) |
| 1999 |
|---|
| 4 | | Mitsuo Ikeda,
Toshio Kondo,
Koyo Nitta,
Kazuhito Suguri,
Takeshi Yoshitome,
Toshihiro Minami,
Jiro Naganuma,
Takeshi Ogura:
An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture.
DATE 1999: 44- |
| 3 | | Tsuneo Okubo,
Mitsuo Ikeda,
Yutaka Tashiro,
Toshio Kondo,
Ryota Kasai,
Hiroshi Kotera,
Tetsuma Sakurai:
Concurrent and collaborative methodologies in short TAT LSI design and manufacturing.
Systems and Computers in Japan 30(7): 79-91 (1999) |
| 1986 |
|---|
| 2 | | Toshio Kondo,
Toshio Tsuchiya,
Yoshihiro Kitamura,
Yoshi Sugiyama,
Takashi Kimura,
Takayoshi Nakashima:
Pseudo MIMD Array Processor - AAP2.
ISCA 1986: 330-337 |
| 1985 |
|---|
| 1 | | Toshio Kondo,
Tayoshi Nakashima,
Toshio Tsuchiya,
Yoshi Sugiyama,
Tsuneta Sudo:
A large scale cellular array processor: AAP-1.
ACM Conference on Computer Science 1985: 100-111 |
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