Avinoam Kolodny

	2012
63		Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer: The complexity of VLSI power-delay optimization by interconnect resizing. J. Comb. Optim. 23(2): 292-300 (2012)
62		Tomer Y. Morad, Avinoam Kolodny, Uri C. Weiser: Task Scheduling Based On Thread Essence and Resource Limitations. JCP 7(1): 53-64 (2012)
61		Victoria Vishnyakov, Eby G. Friedman, Avinoam Kolodny: Multi-aggressor capacitive and inductive coupling noise modeling and mitigation. Microelectronics Journal 43(4): 235-243 (2012)
60		Roman Malits, Evgeny Bolotin, Avinoam Kolodny, Avi Mendelson: Exploring the limits of GPGPU scheduling in control flow bound applications. TACO 8(4): 29 (2012)
	2011
59		Ran Manevich, Israel Cidon, Avinoam Kolodny, Isask'har Walter, Shmuel Wimer: A Cost Effective Centralized Adaptive Routing for Networks-on-Chip. DSD 2011: 39-46
58		Shahar Kvatinsky, Avinoam Kolodny, Uri C. Weiser, Eby G. Friedman: Memristor-based IMPLY logic design procedure. ICCD 2011: 142-147
57		Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin, Avinoam Kolodny: An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm. ISCAS 2011: 2593-2596
56		Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny: Delay analysis of wormhole based heterogeneous NoC. NOCS 2011: 161-168
55		Yaniv Ben-Itzhak, Eitan Zahavi, Israel Cidon, Avinoam Kolodny: NoCs simulation framework for OMNeT++. NOCS 2011: 265-266
54		Evgeni Krimer, Isaac Keslassy, Avinoam Kolodny, Isask'har Walter, Mattan Erez: Static timing analysis for modeling QoS in networks-on-chip. J. Parallel Distrib. Comput. 71(5): 687-699 (2011)
53		Yoni Aizik, Avinoam Kolodny: Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints. VLSI Design 2011: (2011)
	2010
52		Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman: Timing-driven variation-aware nonuniform clock mesh synthesis. ACM Great Lakes Symposium on VLSI 2010: 15-20
51		Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin, Avinoam Kolodny: The Devolution of Synchronizers. ASYNC 2010: 94-103
50		Rudy Beraha, Isask'har Walter, Israel Cidon, Avinoam Kolodny: Leveraging application-level requirements in the design of a NoC for a 4G SoC - a case study. DATE 2010: 1408-1413
49		Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny: Performance and Power Aware CMP Thread Allocation Modeling. HiPEAC 2010: 232-246
48		Zvika Guz, Oved Itzhak, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser: Threads vs. caches: Modeling the behavior of parallel workloads. ICCD 2010: 274-281
47		Gregory Sizikov, Avinoam Kolodny, Eby G. Friedman, Michael Zelikson: Efficiency optimization of integrated DC-DC buck converters. ICECS 2010: 1208-1211
46		Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer: Interconnect power and delay optimization by dynamic programming in gridded design rules. ISPD 2010: 153-160
45		Ran Manevich, Israel Cidon, Avinoam Kolodny, Isask'har Walter: Centralized Adaptive Routing for NoCs. Computer Architecture Letters 9(2): 57-60 (2010)
44		Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny: Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect. IEEE Trans. VLSI Syst. 18(5): 689-696 (2010)
43		Rostislav (Reuven) Dobkin, Michael Moyal, Avinoam Kolodny, Ran Ginosar: Asynchronous Current Mode Serial Communication. IEEE Trans. VLSI Syst. 18(7): 1107-1117 (2010)
42		Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny: Corrections to "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" [May 10 689-696]. IEEE Trans. VLSI Syst. 18(8): 1262 (2010)
41		Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer: Interconnect Bundle Sizing Under Discrete Design Rules. IEEE Trans. on CAD of Integrated Circuits and Systems 29(10): 1650-1654 (2010)
	2009
40		Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman: Power efficient tree-based crosslinks for skew reduction. ACM Great Lakes Symposium on VLSI 2009: 285-290
39		Ran Manevich, Isask'har Walter, Israel Cidon, Avinoam Kolodny: Best of both worlds: A bus enhanced NoC (BENoC). NOCS 2009: 173-182
38		Rudy Beraha, Isask'har Walter, Israel Cidon, Avinoam Kolodny: The design of a latency constrained, power optimized NoC for a 4G SoC. NOCS 2009: 86
37		Evgeni Krimer, Mattan Erez, Isaac Keslassy, Avinoam Kolodny, Isask'har Walter: Packet-level static timing analysis for NoCs. NOCS 2009: 88
36		Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer: Power-delay optimization in VLSI microprocessors by wire spacing. ACM Trans. Design Autom. Electr. Syst. 14(4): (2009)
35		Zvika Guz, Evgeny Bolotin, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser: Many-Core vs. Many-Thread Machines: Stay Away From the Valley. Computer Architecture Letters 8(1): 25-28 (2009)
34		Avinoam Kolodny, Li-Shiuan Peh: Special Section on International Symposium on Networks-on-Chip (NOCS). IEEE Trans. VLSI Syst. 17(3): 317-318 (2009)
33		Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny: QNoC asynchronous router. Integration 42(2): 103-115 (2009)
	2008
32		Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny: Timing optimization in logic with interconnect. SLIP 2008: 19-26
31		Rostislav (Reuven) Dobkin, Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar: Parallel vs. serial on-chip communication. SLIP 2008: 43-50
30		Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser: Utilizing shared data in chip multiprocessors with the nahalal architecture. SPAA 2008: 1-10
29		Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer: Timing-aware power-optimal ordering of signals. ACM Trans. Design Autom. Electr. Syst. 13(4): (2008)
28		I. Walter, Israel Cidon, Avinoam Kolodny: BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP. Computer Architecture Letters 7(2): 61-64 (2008)
27		Mikhail Popovich, Michael Sotman, Avinoam Kolodny, Eby G. Friedman: Effective Radii of On-Chip Decoupling Capacitors. IEEE Trans. VLSI Syst. 16(7): 894-907 (2008)
26		Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny: On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits. IEEE Trans. VLSI Syst. 16(7): 908-921 (2008)
25		Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny: On optimal ordering of signals in parallel wire bundles. Integration 41(2): 253-268 (2008)
	2007
24		Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar, Avinoam Kolodny: High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link. ASYNC 2007: 3-14
23		Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Routing table minimization for irregular mesh NoCs. DATE 2007: 942-947
22		Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny: The Power of Priority: NoC Based Distributed Cache Coherency. NOCS 2007: 117-126
21		Isask'har Walter, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Access Regulation to Hot-Modules in Wormhole NoCs. NOCS 2007: 137-148
20		Avinoam Kolodny: Networks on chips: keeping up with Rent's rule and Moore's law. SLIP 2007: 55-56
19		Michael Behar, Avi Mendelson, Avinoam Kolodny: Trace cache sampling filter. ACM Trans. Comput. Syst. 25(1): (2007)
18		Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser: Nahalal: Cache Organization for Chip Multiprocessors. Computer Architecture Letters 6(1): 21-24 (2007)
17		Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Network Delays and Link Capacities in Application-Specific Wormhole NoCs. VLSI Design 2007: (2007)
	2006
16		Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny, Radu M. Secareanu: Maximum effective distance of on-chip decoupling capacitors in power distribution grids. ACM Great Lakes Symposium on VLSI 2006: 173-179
15		Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny: Fast Asynchronous Shift Register for Bit-Serial Communication. ASYNC 2006: 117-127
14		Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Efficient link capacity and QoS design for network-on-chip. DATE 2006: 9-14
13		Michael Sotman, Avinoam Kolodny, Mikhail Popovich, Eby G. Friedman: On-die decoupling capacitance: frequency domain analysis of activity radius. ISCAS 2006
12		Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny: Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing. ISCAS 2006
11		Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny: Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization. IEEE Trans. VLSI Syst. 14(11): 1276-1281 (2006)
	2005
10		Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny: On-chip power distribution grids with multiple supply voltages for high performance integrated circuits. ACM Great Lakes Symposium on VLSI 2005: 2-7
9		Michael Behar, Avi Mendelson, Avinoam Kolodny: Trace Cache Sampling Filter. IEEE PACT 2005: 255-266
8		Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Low-leakage repeaters for NoC interconnects. ISCAS (1) 2005: 600-603
7		Noam Dolev, Avner Kornfeld, Avinoam Kolodny: Comparison of Sigma-delta Converter Circuit Architectures in Digital Cmos Technology. Journal of Circuits, Systems, and Computers 14(3): 515-532 (2005)
	2004
6		Nir Magen, Avinoam Kolodny, Uri C. Weiser, Nachum Shamir: Interconnect-power dissipation in a microprocessor. SLIP 2004: 7-13
5		Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Cost considerations in network on chip. Integration 38(1): 19-42 (2004)
4		Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny: QNoC: QoS architecture and design process for network on chip. Journal of Systems Architecture 50(2-3): 105-128 (2004)
	2003
3		Arkadiy Morgenshtein, Michael Moreinis, Israel A. Wagner, Avinoam Kolodny: Logic Gates as Repeaters (LGR) for Timing Optimization of SoC Interconnects. VLSI-SOC 2003: 99-104
2		Y. Elboim, Avinoam Kolodny, Ran Ginosar: A clock-tuning circuit for system-on-chip. IEEE Trans. VLSI Syst. 11(4): 616-626 (2003)
1		O. Milter, Avinoam Kolodny: Crosstalk noise reduction in synthesized digital logic circuits. IEEE Trans. VLSI Syst. 11(6): 1153-1158 (2003)

Coauthor Index

1	Ameer Abdelhadi	[52]
2	Yoni Aizik	[53]
3	Salomon Beer	[51] [57]
4	Michael Behar	[9] [19]
5	Yaniv Ben-Itzhak	[49] [55] [56]
6	Rudy Beraha	[38] [50]
7	Evgeny Bolotin	[4] [5] [14] [17] [22] [23] [35] [60]
8	Israel Cidon	[4] [5] [8] [14] [17] [21] [22] [23] [28] [38] [39] [45] [49] [50] [55] [56] [59]
9	Rostislav (Reuven) Dobkin	[15] [24] [31] [33] [43] [51] [57]
10	Noam Dolev	[7]
11	Y. Elboim	[2]
12	Mattan Erez	[37] [54]
13	Eby G. Friedman	[10] [13] [16] [26] [27] [32] [40] [42] [44] [47] [52] [58] [61]
14	Ran Ginosar	[2] [4] [5] [8] [14] [15] [17] [21] [22] [23] [24] [31] [32] [33] [40] [42] [43] [44] [51] [52] [57]
15	Zvika Guz	[14] [17] [18] [22] [30] [35] [48]
16	Oved Itzhak	[48]
17	Idit Keidar	[18] [30] [35] [48]
18	Isaac Keslassy	[37] [54]
19	Avner Kornfeld	[7]
20	Evgeni Krimer	[37] [54]
21	Shahar Kvatinsky	[58]
22	Tuvia Liran	[24]
23	Nir Magen	[6]
24	Roman Malits	[60]
25	Ran Manevich	[39] [45] [59]
26	Avi Mendelson	[9] [19] [35] [48] [60]
27	O. Milter	[1]
28	Konstantin Moiseev	[12] [25] [29] [36] [41] [46] [63]
29	Tomer Y. Morad	[62]
30	Michael Moreinis	[3] [11]
31	Arkadiy Morgenshtein	[3] [8] [11] [31] [32] [42] [44]
32	Michael Moyal	[43]
33	Li-Shiuan Peh	[34]
34	Yevgeny Perelman	[24]
35	Mikhail Popovich	[10] [13] [16] [26] [27]
36	Michael Priel	[51] [57]
37	Radu M. Secareanu	[16]
38	Nachum Shamir	[6]
39	Gregory Sizikov	[47]
40	Michael Sotman	[10] [13] [16] [26] [27]
41	Inna Vaisband	[40]
42	Victoria Vishnyakov	[61]
43	Israel A. Wagner	[3] [11]
44	I. Walter	[28]
45	Isask'har Walter	[14] [17] [21] [37] [38] [39] [45] [50] [54] [59]
46	Uri C. Weiser	[6] [18] [30] [35] [48] [58] [62]
47	Shmuel Wimer	[12] [25] [29] [36] [41] [46] [59] [63]
48	Eitan Zahavi	[55]
49	Michael Zelikson	[47]

Colors in the list of coauthors

Last update Sat Jun 2 20:57:36 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page