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| 2012 | ||
|---|---|---|
| 29 | Shin-ichi O'Uchi, Kazuhiko Endo, Takashi Matsukawa, Yongxun Liu, Tadashi Nakagawa, Yuki Ishikawa, Junichi Tsukada, Hiromi Yamauchi, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara: A 0.7-V Opamp in Scaled Low-Standby-Power FinFET Technology. IEICE Transactions 95-C(4): 686-695 (2012) | |
| 28 | Hideo Sakai, Shin-ichi O'Uchi, Takashi Matsukawa, Kazuhiko Endo, Yongxun Liu, Junichi Tsukada, Yuki Ishikawa, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara, Hiroki Ishikuro: High-Frequency Precise Characterization of Intrinsic FinFET Channel. IEICE Transactions 95-C(4): 752-760 (2012) | |
| 2010 | ||
| 27 | Naoto Miyamoto, Yohei Matsumoto, Hanpei Koike, Tadayuki Matsumura, Kenichi Osada, Yaoko Nakagawa, Tadahiro Ohmi: Development of a CAD tool for 3D-FPGAs. 3DIC 2010: 1-6 | |
| 26 | Shin-ichi O'Uchi, Kazuhiko Endo, Yongxun Liu, Tadashi Nakagawa, Takashi Matsukawa, Yuki Ishikawa, Junichi Tsukada, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara: Realization of 0.7-V analog circuits by adaptive-Vt operation of FinFET. CICC 2010: 1-4 | |
| 2009 | ||
| 25 | Seid Hadi Rasouli, Hanpei Koike, Kaustav Banerjee: High-speed low-power FinFET based domino logic. ASP-DAC 2009: 829-834 | |
| 2008 | ||
| 24 | Shin-ichi O'Uchi, Meishoku Masahara, Kazuhiko Endo, Yongxun Liu, Takashi Matsukawa, Kunihiro Sakamoto, Toshihiro Sekigawa, Hanpei Koike, Eiichi Suzuki: FinFET-Based Flex-Vth SRAM Design for Drastic Standby-Leakage-Current Reduction. IEICE Transactions 91-C(4): 534-542 (2008) | |
| 23 | Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Hanpei Koike, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa: Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations. TRETS 1(1): (2008) | |
| 2007 | ||
| 22 | Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike: Performance and yield enhancement of FPGAs with within-die variation using multiple configurations. FPGA 2007: 169-177 | |
| 21 | Takashi Kawanami, Masakazu Hioki, Yohei Matsumoto, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike: Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGA. IEICE Transactions 90-D(12): 1947-1955 (2007) | |
| 2006 | ||
| 20 | Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike: Evaluation of granularity on threshold voltage control in flex power FPGA. FPGA 2006: 223 | |
| 19 | Yohei Matsumoto, Hanpei Koike, Akira Masaki: FPGAs with multidimensional mesh topology. FPGA 2006: 223 | |
| 2004 | ||
| 18 | Takashi Kawanami, Masakazu Hioki, Hiroshi Nagase, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike: Preliminary performance analysis of flex power FPGA, a power reconfigurable device with fine granularity. FPGA 2004: 257 | |
| 17 | Takashi Kawanami, Masakazu Hioki, Hiroshi Nagase, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike: Preliminary Evaluation of Flex Power FPGA: A Power Reconfigurable Architecture with Fine Granularity. IEICE Transactions 87-D(8): 2004-2010 (2004) | |
| 1998 | ||
| 16 | Hayato Yamana, Hanpei Koike, Yuetsu Kodama, Hirofumi Sakane, Yoshinori Yamaguchi: Fast Speculative Search Engine on the Highly Parallel Computer EM-X. SIGIR 1998: 390 | |
| 1997 | ||
| 15 | Yuetsu Kodama, Hirofumi Sakane, Hanpei Koike, Mitsuhisa Sato, Shuichi Sakai, Yoshinori Yamaguchi: Parallel Execution of Radix Sort Program Using Fine-Grain Communication. IEEE PACT 1997: 136-145 | |
| 1994 | ||
| 14 | Hidemoto Nakada, Takuya Araki, Hanpei Koike, Hidehiko Tanaka: A Fleng Compiler for PIE64. IFIP PACT 1994: 257-266 | |
| 13 | Jun'ichi Tatemura, Hanpei Koike, Hidehiko Tanaka: A Performance Debugger for a Parallel Logic Programming Language Fleng. Theory and Practice of Parallel Programming 1994: 284-299 | |
| 1993 | ||
| 12 | Kentaro Shimada, Hanpei Koike, Hidehiko Tanaka: The Instruction Set Architecture of the Inference Processor UNIRED II. Architectures and Compilation Techniques for Fine and Medium Grain Parallelism 1993: 117-128 | |
| 11 | Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka: Multiple Threads in Cyclic Register Windows. ISCA 1993: 131-142 | |
| 10 | Jun'ichi Tatemura, Hanpei Koike, Hidehiko Tanaka: Control and Data Flow Visualization for Parallel Logic Programs on a Multi-window Debugger HyperDEBU. PARLE 1993: 414-425 | |
| 9 | Kentaro Shimada, Hanpei Koike, Hidehiko Tanaka: UNIRED II: The High Performance Inference Processor for the Parallel Inference Machine PIE64. New Generation Comput. 11(3): 251-269 (1993) | |
| 1992 | ||
| 8 | Kentaro Shimada, Hanpei Koike, Hidehiko Tanaka: UNIRED II: The High Performance Inference Processor for the Parallel Inference Machine PIE64. FGCS 1992: 715-722 | |
| 7 | Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka: Architecture of Parallel Management Kernel for PIE64. PARLE 1992: 685-700 | |
| 6 | Jun'ichi Tatemura, Hanpei Koike, Hidehiko Tanaka: HyperDEBU: A Multiwindow Debugger for Parallel Logic Programs. Programming Environments for Parallel Computing 1992: 87-105 | |
| 1991 | ||
| 5 | Yasuo Hidaka, Hanpei Koike, Jun'ichi Tatemura, Hidehiko Tanaka: A Static Load Partitioning Method based on Execution Profile for Committed Choice Languages. ISLP 1991: 470-484 | |
| 1989 | ||
| 4 | Lu Xu, Hanpei Koike, Hidehiko Tanaka: Distributed Garbage Collection for the Parallel Inference Machine PIE64. IFIP Congress 1989: 1161-1166 | |
| 3 | Lu Xu, Hanpei Koike, Hidehiko Tanaka: Distributed Garbage Collection for the Parallel Inference Engine PIE64. NACLP 1989: 922-941 | |
| 1988 | ||
| 2 | Hanpei Koike, Hidehiko Tanaka: Multi-Context Processing and Data Balancing Mechanism of the Parallel Inference Machine PIE64. FGCS 1988: 970-977 | |
| 1986 | ||
| 1 | Hanpei Koike, Hidehiko Tanaka: Fast Execution Mechanisms of Parallel Inference Engine PIE: PIEpelined Goal Rewriting and Goal Multicasting. LP 1986: 159-169 | |
Colors in the list of coauthors
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