Tetsushi Koide

	2011
56		Fengwei An, Hans Jürgen Mattausch, Tetsushi Koide: Real-time hybrid learning and recognition system with software-hardware cooperation. ROBIO 2011: 2505-2510
55		Ali Ahmadi, Hans Jürgen Mattausch, Md. Anwarul Abedin, Mahmoud Saeidi, Tetsushi Koide: An associative memory-based learning model with an efficient hardware implementation in FPGA. Expert Syst. Appl. 38(4): 3499-3513 (2011)
54		Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Masaharu Tagami, Masakatsu Ishizaki: Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems. IEICE Transactions 94-D(9): 1742-1754 (2011)
53		Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Tetsu Nishijima, Tetsushi Tanizaki, Hiroyuki Yamasaki, Takeaki Sugimura, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Kan Murata, Kanako Yoshida, Eisuke Shimomura, Hideyuki Noda, Yoshihiro Okuno, Shunsuke Kamijo, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto: A Scalable Massively Parallel Processor for Real-Time Image Processing. J. Solid-State Circuits 46(10): 2363-2373 (2011)
	2010
52		Tetsushi Koide, R. Kimura, T. Sugahara, K. Okazaki, Hans Jürgen Mattausch: Architecture and FPGA-Implementation of Scalable Picture Segmentation by 2D Scanning with Flexible Pixel-Block Size. ICNC 2010: 128-132
51		Akio Kawabata, Tetsushi Koide, Hans Jürgen Mattausch: Optimization Vector Quantization by Adaptive Associative-Memory-Based Codebook Learning in Combination with Huffman Coding. ICNC 2010: 15-19
50		Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Takayuki Gyohten, Tetsu Nishijima, Hiroyuki Yamasaki, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Yoshihiro Okuno, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto: A scalable massively parallel processor for real-time image processing. ISSCC 2010: 334-335
49		Koh Johguchi, Akihiro Kaya, Shinya Izumi, Hans Jürgen Mattausch, Tetsushi Koide, Norio Sadachika: Measurement-Based Ring Oscillator Variation Analysis. IEEE Design & Test of Computers 27(5): 6-13 (2010)
	2008
48		Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Takayuki Gyohten, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito: Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor. IEICE Transactions 91-C(9): 1409-1418 (2008)
	2007
47		Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito: Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. ISCAS 2007: 525-528
46		Md. Anwarul Abedin, Yuki Tanaka, Ali Ahmadi, Shogo Sakakibara, Tetsushi Koide, Hans Jürgen Mattausch: Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories. IEICE Transactions 90-A(6): 1240-1243 (2007)
45		Koh Johguchi, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka: 4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words. IEICE Transactions 90-C(11): 2157-2160 (2007)
44		Takeshi Kumaki, Yasuto Kuroda, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito: Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer. IEICE Transactions 90-D(1): 334-345 (2007)
43		Takeshi Kumaki, Yutaka Kono, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch: Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory. IEICE Transactions 90-D(1): 346-354 (2007)
42		Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito: Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor. IEICE Transactions 90-D(8): 1312-1315 (2007)
	2006
41		Koh Johguchi, Zhaomin Zhu, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka, Kazuya Tanigawa: Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline. APCCAS 2006: 1297-1300
40		Md. Anwarul Abedin, Yuki Tanaka, Ali Ahmadi, Tetsushi Koide, Hans Jürgen Mattausch: Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search. APCCAS 2006: 1309-1312
39		Takeshi Kumaki, Y. Kouno, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch: Application of Multi-ported CAM for Parallel Coding. APCCAS 2006: 1859-1862
38		Takashi Morimoto, Hidekazu Adachi, K. Yamaoka, K. Awane, Tetsushi Koide, Hans Jürgen Mattausch: An FPGA-Based Region-Growing Video Segmentation System with Boundary-Scan-Only LSI Architecture. APCCAS 2006: 944-947
37		K. Yamaoka, Takashi Morimoto, Hidekazu Adachi, Tetsushi Koide, Hans Jürgen Mattausch: Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking. ASP-DAC 2006: 176-181
36		K. Yamaoka, Takashi Morimoto, Hidekazu Adachi, K. Awane, Tetsushi Koide, Hans Jürgen Mattausch: Multi-object tracking VLSI architecture using image-scan based region growing and feature matching. ISCAS 2006
35		Hideyuki Noda, Katsumi Dosaka, Hans Jürgen Mattausch, Tetsushi Koide, Fukashi Morishita, Kazutami Arimoto: A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC. IEICE Transactions 89-C(11): 1612-1619 (2006)
34		Takashi Morimoto, Hidekazu Adachi, Osamu Kiriyama, Tetsushi Koide, Hans Jürgen Mattausch: Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video-Segmentation. IEICE Transactions 89-D(3): 1299-1302 (2006)
	2005
33		Takashi Morimoto, Osamu Kiriyama, Hidekazu Adachi, Zhaomin Zhu, Tetsushi Koide, Hans Jürgen Mattausch: A low-power video segmentation LSI with boundary-active-only architecture. ASP-DAC 2005: 13-14
32		Ali Ahmadi, Md. Anwarul Abedin, Hans Jürgen Mattausch, Tetsushi Koide: A parallel hardware design for parametric active contour models. AVSS 2005: 609-613
31		Takashi Morimoto, Osamu Kiriyama, Yohmei Harada, Hidekazu Adachi, Tetsushi Koide, Hans Jürgen Mattausch: Object tracking in video pictures based on image segmentation and pattern matching. ISCAS (4) 2005: 3215-3218
30		T. Saito, M. Maeda, Tetsuo Hironaka, Kazuya Tanigawa, Tetsuya Sueyoshi, K. Aoyama, Tetsushi Koide, Hans Jürgen Mattausch: Design of superscalar processor with multi-bank register file. ISCAS (4) 2005: 3507-3510
29		Takeshi Kumaki, Yasuto Kuroda, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito: CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]. ISCAS (5) 2005: 5202-5205
28		Hideyuki Noda, Kazunari Inoue, Hans Jürgen Mattausch, Tetsushi Koide, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara: Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh. IEICE Transactions 88-C(4): 622-629 (2005)
27		Kazunari Inoue, Hideyuki Noda, Kazutami Arimoto, Hans Jürgen Mattausch, Tetsushi Koide: A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features. IEICE Transactions 88-C(6): 1332-1342 (2005)
26		Takahiro Sasaki, Tomohiro Inoue, Nobuhiko Omori, Tetsuo Hironaka, Hans Jürgen Mattausch, Tetsushi Koide: Chip size and performance evaluations of shared cache for on-chip multiprocessor. Systems and Computers in Japan 36(9): 1-13 (2005)
	2004
25		Takashi Morimoto, Yohmei Harada, Tetsushi Koide, Hans Jürgen Mattausch: 350nm CMOS test-chip for architecture verification of real-time QVGA color-video segmentation at the 90nm technology node. ASP-DAC 2004: 531-532
24		Yuji Yano, Tetsushi Koide, Hans Jürgen Mattausch: Associative memory with fully parallel nearest-Manhattan-distance search for low-power real-time single-chip applications. ASP-DAC 2004: 543-544
23		Tetsuya Sueyoshi, Hiroshi Uchida, Hans Jürgen Mattausch, Tetsushi Koide, Yosuke Mitani, Tetsuo Hironaka: Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processors. ASP-DAC 2004: 551-552
22		Takashi Morimoto, Yohmei Harada, Tetsushi Koide, Hans Jürgen Mattausch: Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation. IEICE Transactions 87-D(2): 500-503 (2004)
	2002
21		Shigeki Takekawa, Shin'ichi Wakabayashi, Tetsushi Koide: A coterie-based mutual exclusion algorithm for distributed systems allowing multiple process failures at arbitrary time. Systems and Computers in Japan 33(12): 87-96 (2002)
	2001
20		Tetsushi Koide, S. Shinmori, H. Ishii: Topological optimization with a network reliability constraint. Discrete Applied Mathematics 115(1-3): 135-149 (2001)
19		Koichi Hatta, Shin'ichi Wakabayashi, Tetsushi Koide: Adaptation of genetic operators and parameters of a genetic algorithm based on the elite degree of an individual. Systems and Computers in Japan 32(1): 29-37 (2001)
	2000
18		Shin'ichi Wakabayashi, Tetsushi Koide, Nayoshi Toshine, Masataka Yamane, Hajime Ueno: Genetic algorithm accelerator GAA-II. ASP-DAC 2000: 9-10
17		Takahiro Deguchi, Tetsushi Koide, Shin'ichi Wakabayashi: Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer. ASP-DAC 2000: 99-104
	1999
16		Koichi Hatta, Shin'ichi Wakabayashi, Tetsushi Koide: Solving the Rectangular Packing Problem by an Adaptive GA Based on Sequence-Pair. ASP-DAC 1999: 181-184
15		Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Mutsuaki Goto, Yoshikatsu Nakayama, Koichi Hatta: An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection. ASP-DAC 1999: 37-40
14		Tetsushi Koide, Shin'ichi Wakabayashi: A timing-driven floorplanning algorithm with the Elmore delay model for building block layout. Integration 27(1): 57-76 (1999)
	1998
13		Tetsushi Koide, Shin'ichi Wakabayashi: A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout. ASP-DAC 1998: 577-583
12		Koichi Hatta, Masashige Suzuki, Shin'ichi Wakabayashi, Tetsushi Koide: Solving the Capacitor Placement Problem in a Radial Distribution System Using an Adaptive Genetic Algorithm. PPSN 1998: 1028-1037
	1997
11		Tetsushi Koide, Shin'ichi Wakabayashi, Mitsuhiro Ono, Yutaka Nishimaru, Noriyoshi Yoshida: A timing-driven placement algorithm with the Elmore delay model for row-based VLSIs. Integration 24(1): 53-77 (1997)
	1996
10		Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida: Pin assignment with global routing for VLSI building block layout. IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1575-1583 (1996)
9		Tetsushi Koide, Masahiro Tsuchiya, Shin'ichi Wakabayashi, Noriyoshi Yoshida: A three-layer over-the-cell multi-channel router for a new cell model. Integration 21(3): 171-189 (1996)
	1995
8		Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru: A new performance driven placement method with the Elmore delay model for row based VLSIs. ASP-DAC 1995
7		Yoshinori Katsura, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida: A new system partitioning method under performance and physical constraints for multi-chip modules. ASP-DAC 1995
6		Masahiro Tsuchiya, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida: A three-layer over-cell multi-channel routing method for a new cell model. ASP-DAC 1995
5		Toshihiro Nakaoa, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida: A Verification Algorithm for Logic Circuits with Internal Variables. ISCAS 1995: 1920-1923
4		Tetsuya Miyoshi, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida: An MCM Routing Algorithm Considering Crosstalk. ISCAS 1995: 211-214
	1994
3		Tetsushi Koide, Yoshinori Katsura, Katsumi Yamatani, Shin'ichi Wakabayashi, Noriyoshi Yoshida: A Floorplanning Method with Topological Constraint Manipulation. ISCAS 1994: 165-168
2		Shin'ichi Wakabayashi, Kazunori Isomoto, Tetsushi Koide, Noriyoshi Yoshida: A Systolic Graph Partitioning Algorithm for VLSI Design. ISCAS 1994: 225-228
	1993
1		Shin'ichi Wakabayashi, Hiroshi Kusumoto, Hideki Mishima, Tetsushi Koide, Noriyoshi Yoshida: Gate Array Placement Based on Mincut, Partitioning with Path Delay Constraints. ISCAS 1993: 2059-2062

Coauthor Index

1	Md. Anwarul Abedin	[32] [40] [46] [55]
2	Hidekazu Adachi	[31] [33] [34] [36] [37] [38]
3	Ali Ahmadi	[32] [40] [46] [55]
4	Fengwei An	[56]
5	Kenji Anami	[28]
6	K. Aoyama	[30]
7	Kazutami Arimoto	[27] [28] [29] [35] [42] [44] [47] [48] [50] [53]
8	K. Awane	[36] [38]
9	Takahiro Deguchi	[17]
10	Katsumi Dosaka	[28] [29] [35] [42] [44] [47] [48]
11	Kazuyasu Fujishima	[28]
12	Mutsuaki Goto	[15]
13	Takayuki Gyohten	[48] [50]
14	Yohmei Harada	[22] [25] [31]
15	Masaru Haraguchi	[50] [53]
16	Koichi Hatta	[12] [15] [16] [19]
17	Tetsuo Hironaka	[23] [26] [30] [41] [45]
18	Yuta Imai	[50] [53]
19	Kazunari Inoue	[27] [28]
20	Tomohiro Inoue	[26]
21	H. Ishii	[20]
22	Masakatsu Ishizaki	[39] [42] [43] [44] [48] [50] [53] [54]
23	Kazunori Isomoto	[2]
24	Shinya Izumi	[49]
25	Koh Johguchi	[41] [45] [49]
26	Shunsuke Kamijo	[53]
27	Yoshinori Katsura	[3] [7]
28	Akio Kawabata	[51]
29	Akihiro Kaya	[49]
30	R. Kimura	[52]
31	Osamu Kiriyama	[31] [33] [34]
32	Yutaka Kono	[43]
33	Y. Kouno	[39]
34	Takeshi Kumaki	[29] [39] [42] [43] [44] [47] [48] [50] [53] [54]
35	Takashi Kurafuji	[50] [53]
36	Yasuto Kuroda	[29] [42] [44] [47] [48]
37	Hiroshi Kusumoto	[1]
38	M. Maeda	[30]
39	Hans Jürgen Mattausch	[22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [37] [38] [39] [40] [41] [42] [43] [44] [45] [46] [47] [48] [49] [50] [51] [52] [53] [54] [55] [56]
40	Hideki Mishima	[1]
41	Yosuke Mitani	[23]
42	Tetsuya Miyoshi	[4]
43	Takashi Morimoto	[22] [25] [31] [33] [34] [36] [37] [38]
44	Fukashi Morishita	[35]
45	Kan Murata	[53]
46	Masami Nakajima	[50] [53]
47	Toshihiro Nakaoa	[5]
48	Yoshikatsu Nakayama	[15]
49	Tetsu Nishijima	[50] [53]
50	Yutaka Nishimaru	[8] [11]
51	Hideyuki Noda	[27] [28] [29] [35] [42] [44] [47] [48] [53]
52	K. Okazaki	[52]
53	Yoshihiro Okuno	[50] [53]
54	Nobuhiko Omori	[26]
55	Mitsuhiro Ono	[8] [11]
56	Norio Sadachika	[49]
57	Mahmoud Saeidi	[55]
58	Kazunori Saito	[29] [42] [44] [47] [48]
59	T. Saito	[30]
60	Shogo Sakakibara	[46]
61	Takahiro Sasaki	[26]
62	Eisuke Shimomura	[53]
63	S. Shinmori	[20]
64	Tetsuya Sueyoshi	[23] [30]
65	T. Sugahara	[52]
66	Takeaki Sugimura	[53]
67	Masashige Suzuki	[12]
68	Masaharu Tagami	[54]
69	Shigeki Takekawa	[21]
70	Yuki Tanaka	[40] [46]
71	Kazuya Tanigawa	[30] [41]
72	Tetsushi Tanizaki	[53]
73	Naoyoshi Toshine	[15]
74	Nayoshi Toshine	[18]
75	Masahiro Tsuchiya	[6] [9]
76	Hiroshi Uchida	[23]
77	Hajime Ueno	[18]
78	Shin'ichi Wakabayashi	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [21]
79	Masataka Yamane	[18]
80	K. Yamaoka	[36] [37] [38]
81	Hiroyuki Yamasaki	[50] [53]
82	Katsumi Yamatani	[3]
83	Yuji Yano	[24]
84	Kanako Yoshida	[53]
85	Noriyoshi Yoshida	[1] [2] [3] [4] [5] [6] [7] [9] [10] [11]
86	Tsutomu Yoshihara	[28]
87	Zhaomin Zhu	[33] [41]

Colors in the list of coauthors

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