Michihiro Koibuchi

	2012
65		Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano: A multi-Vdd dynamic variable-pipeline on-chip router for CMPs. ASP-DAC 2012: 407-412
64		Jose Flich, Tor Skeie, Andres Mejia, Olav Lysne, Pedro López, Antonio Robles, José Duato, Michihiro Koibuchi, Tomas Rokicki, José Carlos Sancho: A Survey and Evaluation of Topology-Agnostic Deterministic Routing Algorithms. IEEE Trans. Parallel Distrib. Syst. 23(3): 405-425 (2012)
	2011
63		Michihiro Koibuchi, Takafumi Watanabe, Atsushi Minamihata, Masahiro Nakao, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano: Performance Evaluation of Power-Aware Multi-tree Ethernet for HPC Interconnects. ICNC 2011: 50-57
62		Hiroki Matsutani, Yasuhiro Take, Daisuke Sasaki, Masayuki Kimura, Yuki Ono, Yukinori Nishiyama, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano: A vertical bubble flow network using inductive-coupling for 3-D CMPs. NOCS 2011: 49-56
61		Daihan Wang, Michihiro Koibuchi, Tomohiro Yoneda, Hiroki Matsutani, Hideharu Amano: A Dynamic Link-Width Optimization for Network-on-Chip. RTCSA (2) 2011: 106-108
60		Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga: Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors. IEEE Trans. Computers 60(6): 783-799 (2011)
59		Michihiro Koibuchi, Tomohiro Otsuka, Tomohiro Kudoh, Hideharu Amano: A Switch-Tagged Routing Methodology for PC Clusters with VLAN Ethernet. IEEE Trans. Parallel Distrib. Syst. 22(2): 217-230 (2011)
58		Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano: Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs. IEEE Trans. on CAD of Integrated Circuits and Systems 30(4): 520-533 (2011)
57		Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga: An Efficient Path Setup for a Hybrid Photonic Network-on-Chip. IJNC 1(2): 244-259 (2011)
56		Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano: An analytical network performance model for SIMD processor CSX600 interconnects. Journal of Systems Architecture - Embedded Systems Design 57(1): 146-159 (2011)
	2010
55		Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga: An Efficient Path Setup for a Photonic Network-on-Chip. ICNC 2010: 156-161
54		Yasutsugu Nagatomi, Michihiro Koibuchi, Hideyuki Kawashima, Koichi Inoue, Hiroaki Nishi: A Regular Expression Processor Embedded in Service-Friendly Router for Future Internet. ICPP Workshops 2010: 82-88
53		José Miguel Montañana Aliaga, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano: Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks. NAS 2010: 218-227
52		Yuri Nishikawa, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano: A Deadlock-Free Non-minimal Fully Adaptive Routing Using Virtual Cut-Through Switching. NAS 2010: 431-438
51		Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano: Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs. NOCS 2010: 61-68
50		Tomoaki Makino, Koichi Inoue, Michihiro Koibuchi, Hideyuki Kawashima, Hiroaki Nishi: Hardware Architecture for Supporting High-speed Database Insertion on Service-oriented Router for Future Internet. PDPTA 2010: 402-407
49		Shigeo Urushidani, Kensuke Fukuda, Michihiro Koibuchi, Motonori Nakamura, Shunji Abe, Yusheng Ji, Michihiro Aoki, Shigeki Yamada: Dynamic Resource Allocation and QoS Control Capabilities of the Japanese Academic Backbone Network. Future Internet 2(3): 295-307 (2010)
	2009
48		Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga: Prediction router: Yet another low latency on-chip router architecture. HPCA 2009: 367-378
47		Shigeo Urushidani, Kensuke Fukuda, Yusheng Ji, Michihiro Koibuchi, Shunji Abe, Motonori Nakamura, Shigeki Yamada, Kaori Shimizu, Rie Hayashi, Ichiro Inoue, Kohei Shiomoto: Implementation and Evaluation of Layer-1 Bandwidth-on-Demand Capabilities in SINET3. ICC 2009: 1-6
46		José Miguel Montañana Aliaga, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano: Balanced Dimension-Order Routing for k-ary n-cubes. ICPP Workshops 2009: 499-506
45		Michihiro Koibuchi, Tomohiro Otsuka, Hiroki Matsutani, Hideharu Amano: An on/off link activation method for low-power ethernet in PC clusters. IPDPS 2009: 1-11
44		Tomoyuki Hiroyasu, Kozo Kawasaki, Michihiro Koibuchi, Shigeo Urushidani, Mitsunori Miki, Masato Yoshimi: Efficient Scheduling Algorithms on Bandwidth Reservation Service of Internet Using Metaheuristics. ISDA 2009: 683-688
43		Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Akihiro Shitara, Kenichi Miura, Hideharu Amano: Performance Analysis of ClearSpeed's CSX600 Interconnects. ISPA 2009: 203-210
42		José Miguel Montañana Aliaga, Michihiro Koibuchi, Takafumi Watanabe, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano: An On/Off Link Activation Method for Power Regulation in InfiniBand. PDPTA 2009: 289-295
41		Shigeo Urushidani, Shunji Abe, Yusheng Ji, Kensuke Fukuda, Michihiro Koibuchi, Motonori Nakamura, Shigeki Yamada, Kaori Shimizu, Rie Hayashi, Ichiro Inoue, Kohei Shiomoto: Design of versatile academic infrastructure for multilayer network services. IEEE Journal on Selected Areas in Communications 27(3): 253-267 (2009)
40		Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, D. Frank Hsu, Hideharu Amano: Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network. IEEE Trans. Parallel Distrib. Syst. 20(8): 1126-1141 (2009)
39		Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs. IEICE Transactions 92-D(4): 575-583 (2009)
38		Jumpot Phuritatkul, Kien Nguyen, Michihiro Koibuchi, Yusheng Ji, Kensuke Fukuda, Shunji Abe, Jun Matsukata, Shigeo Urushidani, Shigeki Yamada: Impact of QoS operations on an experimental testbed network. Simulation Modelling Practice and Theory 17(3): 528-537 (2009)
	2008
37		Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Daihan Wang: Run-time power gating of on-chip routers using look-ahead routing. ASP-DAC 2008: 55-60
36		Takafumi Watanabe, Masahiro Nakao, Tomoyuki Hiroyasu, Tomohiro Otsuka, Michihiro Koibuchi: Impact of topology and link aggregation on a PC cluster with Ethernet. CLUSTER 2008: 280-285
35		Daihan Wang, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi: A link removal methodology for Networks-on-Chip on reconfigurable systems. FPL 2008: 269-274
34		Hiroki Matsutani, Michihiro Koibuchi, D. Frank Hsu, Hideharu Amano: Three-Dimensional Layout of On-Chip Tree-Based Networks. ISPAN 2008: 281-288
33		Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy Mark Pinkston: A Lightweight Fault-Tolerant Mechanism for Network-on-Chip. NOCS 2008: 13-22
32		Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano: Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks. NOCS 2008: 23-32
	2007
31		Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems. FPL 2007: 383-388
30		Shigeo Urushidani, Jun Matsukata, Kensuke Fukuda, Shunji Abe, Yusheng Ji, Michihiro Koibuchi, Shigeki Yamada, Kaori Shimizu, Tomonori Takeda, Ichiro Inoue, Kohei Shiomoto: Layer-1 Bandwidth on Demand Services in SINET3. GLOBECOM 2007: 2286-2291
29		Jumpot Phuritatkul, Kien Nguyen, Michihiro Koibuchi, Yusheng Ji: Investigating QoS Performance on a Testbed Network. ICCCN 2007: 1267-1272
28		Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: Tightly-Coupled Multi-Layer Topologies for 3-D NoCs. ICPP 2007: 75
27		Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano: Performance Improvement Methodology for ClearSpeed's CSX600. ICPP 2007: 77
26		Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network. IPDPS 2007: 1-10
25		Akiya Jouraku, Michihiro Koibuchi, Hideharu Amano: An Effective Design of Deadlock-Free Routing Algorithms Based on 2D Turn Model for Irregular Networks. IEEE Trans. Parallel Distrib. Syst. 18(3): 320-333 (2007)
24		Shigeo Urushidani, Shunji Abe, Kensuke Fukuda, Jun Matsukata, Yusheng Ji, Michihiro Koibuchi, Shigeki Yamada: Architectural Design of Next-Generation Science Information Network. IEICE Transactions 90-B(5): 1061-1070 (2007)
23		Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs. IEICE Transactions 90-D(12): 1914-1922 (2007)
	2006
22		Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Michihiro Koibuchi, Hideharu Amano: A Parametric Study of Scalable Interconnects on FPGAs. ERSA 2006: 130-135
21		Tomohiro Otsuka, Michihiro Koibuchi, Tomohiro Kudoh, Hideharu Amano: Switch-tagged VLAN Routing Methodology for PC Clusters with Ethernet. ICPP 2006: 479-486
20		Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks. ISCA PDCS 2006: 24-31
19		Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: Enforcing Dimension-Order Routing in On-Chip Torus Networks Without Virtual Channels. ISPA 2006: 207-218
18		Michihiro Koibuchi, Kenichiro Anjo, Yutaka Yamada, Akiya Jouraku, Hideharu Amano: A Simple Data Transfer Technique Using Local Address for Networks-on-Chips. IEEE Trans. Parallel Distrib. Syst. 17(12): 1425-1437 (2006)
	2005
17		Tomohiro Otsuka, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano: VLAN-Based Minimal Paths in PC Cluster with Ethernet on Mesh and Torus. ICPP 2005: 567-576
16		Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Akiya Jouraku, Hideharu Amano: Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips. ICPP Workshops 2005: 273-280
15		Juan Carlos Martínez, Jose Flich, Antonio Robles, Pedro López, José Duato, Michihiro Koibuchi: In-Order Packet Delivery in Interconnection Networks using Adaptive Routing. IPDPS 2005
14		Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: Destination Bundle: A Routing Table Reduction Technique for Distributed Routing on Dependable Networks-on-Chips. PDPTA 2005: 1343-1349
13		Michihiro Koibuchi, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano: Performance Evaluation of Deterministic Routings, Multicasts, and Topologies on RHiNET-2 Cluster. IEEE Trans. Parallel Distrib. Syst. 16(8): 747-759 (2005)
12		Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano: MMLRU Selection Function: A Simple and Efficient Output Selection Function in Adaptive Routing. IEICE Transactions 88-D(1): 109-118 (2005)
11		Michihiro Koibuchi, Juan Carlos Martínez, Jose Flich, Antonio Robles, Pedro López, José Duato: Enforcing in-order packet delivery in system area networks with adaptive routing. J. Parallel Distrib. Comput. 65(10): 1223-1236 (2005)
10		Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano: Path selection algorithm: the strategy for designing deterministic routing from alternative paths. Parallel Computing 31(1): 117-130 (2005)
	2004
9		Yutaka Yamada, Hideharu Amano, Michihiro Koibuchi, Akiya Jouraku, Kenichiro Anjo, Katsunobu Nishimura: Folded Fat H-Tree: An Interconnection Topology for Dynamically Reconfigurable Processor Array. EUC 2004: 301-311
8		Kenichiro Anjo, Yutaka Yamada, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano: BLACK-BUS: A New Data-Transfer Technique Using Local Address on Networks-on-Chips. IPDPS 2004
	2003
7		Michihiro Koibuchi, Konosuke Watanabe, Kenichi Kono, Akiya Jouraku, Hideharu Amano: Performance Evaluation of Routing Algorithms in RHiNET-2 Cluster. CLUSTER 2003: 395-
6		Michihiro Koibuchi, Akiya Jouraku, Konosuke Watanabe, Hideharu Amano: Descending Layers Routing: A Deadlock-Free Deterministic Routing using Virtual Channels in System Area Networks with Irregular Topologies. ICPP 2003: 527-
	2002
5		Akiya Jouraku, Michihiro Koibuchi, Hideharu Amano, Akira Funahashi: Routing Algorithms Based on 2D Turn Model for Irregular Networks. ISPAN 2002: 289-294
4		Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano: The Impact of Path Selection Algorithm of Adaptive Routing for Implementing Deterministic Routing. PDPTA 2002: 1431-1437
	2001
3		Akira Funahashi, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano: The impact of output selection function on adaptive routing. Computers and Their Applications 2001: 241-246
2		Michihiro Koibuchi, Akira Funahashi, Akiya Jouraku, Hideharu Amano: L-Turn Routing: An Adaptive Routing in Irregular Networks. ICPP 2001: 383-392
1		Michihiro Koibuchi, Akiya Jouraku, Akira Funahashi, Hideharu Amano: MMLRU Selection Function: An Output Selection Function on Adaptive Routing. ISCA PDCS 2001: 1-6

Coauthor Index

1	Shunji Abe	[24] [30] [38] [41] [47] [49]
2	Cisse Ahmadou Dit Adi	[55] [57]
3	Hideharu Amano	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [12] [13] [14] [16] [17] [18] [19] [20] [21] [22] [23] [25] [26] [27] [28] [31] [32] [33] [34] [35] [37] [39] [40] [42] [43] [45] [46] [48] [51] [52] [53] [56] [58] [59] [60] [61] [62] [63] [65]
4	Kenichiro Anjo	[8] [9] [18]
5	Michihiro Aoki	[49]
6	José Duato (José Duato Marín)	[11] [15] [64]
7	Jose Flich (José Flich)	[11] [15] [64]
8	Kensuke Fukuda	[24] [30] [38] [41] [47] [49]
9	Akira Funahashi	[1] [2] [3] [5]
10	Rie Hayashi	[41] [47]
11	Yuto Hirata	[65]
12	Tomoyuki Hiroyasu	[36] [42] [44] [63]
13	D. Frank Hsu	[34] [40]
14	Daisuke Ikebuchi	[51] [58]
15	Ichiro Inoue	[30] [41] [47]
16	Koichi Inoue	[50] [54]
17	Hidetsugu Irie	[55] [57]
18	Yusheng Ji	[24] [29] [30] [38] [41] [47] [49]
19	Akiya Jouraku	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [12] [16] [17] [18] [25]
20	Kozo Kawasaki	[44]
21	Hideyuki Kawashima	[50] [54]
22	Masayuki Kimura	[62]
23	Kenichi Kono	[7]
24	Tomohiro Kudoh	[21] [59]
25	Tadahiro Kuroda	[62]
26	Pedro López (Pedro Juan López Rodríguez)	[11] [15] [64]
27	Olav Lysne	[64]
28	Tomoaki Makino	[50]
29	Juan Carlos Martínez	[11] [15]
30	Jun Matsukata	[24] [30] [38]
31	Hiroki Matsutani	[14] [16] [19] [20] [22] [23] [26] [28] [31] [32] [33] [34] [35] [37] [39] [40] [42] [45] [46] [48] [51] [52] [53] [55] [57] [58] [60] [61] [62] [63] [65]
32	Andres Mejia	[64]
33	Mitsunori Miki	[44]
34	Atsushi Minamihata	[63]
35	Kenichi Miura	[27] [43] [56]
36	Takefumi Miyoshi	[55] [57]
37	José Miguel Montañana (José Miguel Montañana Aliaga)	[42] [46] [53]
38	Yasutsugu Nagatomi	[54]
39	Hiroshi Nakamura	[51] [58] [65]
40	Motonori Nakamura	[41] [47] [49]
41	Masahiro Nakao	[36] [63]
42	Kien Nguyen	[29] [38]
43	Hiroaki Nishi	[50] [54]
44	Yuri Nishikawa	[27] [43] [52] [56]
45	Katsunobu Nishimura	[9]
46	Yukinori Nishiyama	[62]
47	Yuki Ono	[62]
48	Tomohiro Otsuka	[13] [17] [21] [36] [45] [59]
49	Jumpot Phuritatkul	[29] [38]
50	Timothy Mark Pinkston	[33]
51	Antonio Robles	[11] [15] [64]
52	Tomas Rokicki	[64]
53	José Carlos Sancho	[64]
54	Daisuke Sasaki	[62]
55	Kaori Shimizu	[30] [41] [47]
56	Kohei Shiomoto	[30] [41] [47]
57	Akihiro Shitara	[43]
58	Tor Skeie	[64]
59	Yasuhiro Take	[62]
60	Tomonori Takeda	[30]
61	Shigeo Urushidani	[24] [30] [38] [41] [44] [47] [49]
62	Kimiyoshi Usami	[51] [58] [65]
63	Daihan Wang	[22] [23] [31] [32] [35] [37] [39] [61]
64	Konosuke Watanabe	[6] [7] [13]
65	Takafumi Watanabe	[36] [42] [63]
66	Shigeki Yamada	[24] [30] [38] [41] [47] [49]
67	Yutaka Yamada	[8] [9] [16] [18] [40]
68	Tomohiro Yoneda	[61]
69	Masato Yoshimi	[22] [27] [43] [44] [56]
70	Tsutomu Yoshinaga	[48] [55] [57] [60]

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