Yukihide Kohira

	2012
15		Yukihide Kohira, Atsushi Takahashi: An any-angle routing method using quasi-Newton method. ASP-DAC 2012: 145-150
	2011
14		Kyosuke Shinoda, Yukihide Kohira, Atsushi Takahashi: Single-Layer Trunk Routing Using Minimal 45-Degree Lines. IEICE Transactions 94-A(12): 2510-2518 (2011)
	2010
13		Yukihide Kohira, Atsushi Takahashi: CAFE router: a fast connectivity aware multiple nets routing algorithm for routing grid with obstacles. ASP-DAC 2010: 281-286
12		Yukihide Kohira, Atsushi Takahashi: CAFE Router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles. IEICE Transactions 93-A(12): 2380-2388 (2010)
	2009
11		Yukihide Kohira, Suguru Suehiro, Atsushi Takahashi: A fast longer path algorithm for routing grid with obstacles using biconnectivity based length upper bound. ASP-DAC 2009: 600-605
10		Yukihide Kohira, Suguru Suehiro, Atsushi Takahashi: A Fast Longer Path Algorithm for Routing Grid with Obstacles Using Biconnectivity Based Length Upper Bound. IEICE Transactions 92-A(12): 2971-2978 (2009)
9		Yoichi Tomioka, Yoshiaki Kurata, Yukihide Kohira, Atsushi Takahashi: MILP-Based Efficient Routing Method with Restricted Route Structure for 2-Layer Ball Grid Array Packages. IEICE Transactions 92-A(12): 2998-3006 (2009)
8		Yukihide Kohira, Shuhei Tani, Atsushi Takahashi: Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework. IEICE Transactions 92-A(4): 1106-1114 (2009)
	2008
7		Yukihide Kohira, Atsushi Takahashi: A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework. IEICE Transactions 91-A(10): 3030-3037 (2008)
6		Yosuke Takahashi, Yukihide Kohira, Atsushi Takahashi: A Fast Clock Scheduling for Peak Power Reduction in LSI. IEICE Transactions 91-A(12): 3803-3811 (2008)
	2007
5		Yosuke Takahashi, Yukihide Kohira, Atsushi Takahashi: A fast clock scheduling for peak power reduction in LSI. ACM Great Lakes Symposium on VLSI 2007: 582-587
4		Yukihide Kohira, Atsushi Takahashi: A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework. ISCAS 2007: 1795-1798
3		Yukihide Kohira, Atsushi Takahashi: Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization. IEICE Transactions 90-A(4): 800-807 (2007)
	2006
2		Yukihide Kohira, Chikaaki Kodama, Kunihiro Fujiyoshi, Atsushi Takahashi: Evaluation of 3D-packing representations for scheduling of dynamically reconfigurable systems. ISCAS 2006
	2005
1		Yukihide Kohira, Atsushi Takahashi: Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion. IEICE Transactions 88-A(4): 892-898 (2005)

Coauthor Index

1	Kunihiro Fujiyoshi	[2]
2	Chikaaki Kodama	[2]
3	Yoshiaki Kurata	[9]
4	Kyosuke Shinoda	[14]
5	Suguru Suehiro	[10] [11]
6	Atsushi Takahashi	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
7	Yosuke Takahashi	[5] [6]
8	Shuhei Tani	[8]
9	Yoichi Tomioka	[9]

Last update Sun Jun 3 16:06:10 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page