 | 2012 |
| 20 |  | Shinya Takamaeda-Yamazaki,
Shintaro Sano,
Yoshito Sakaguchi,
Naoki Fujieda,
Kenji Kise:
ScalableCore System: A Scalable Many-Core Simulator by Employing over 100 FPGAs.
ARC 2012: 138-150 |
| 19 |  | Tomoyuki Nagatsuka,
Yoshito Sakaguchi,
Kenji Kise:
CoreSymphony architecture.
Conf. Computing Frontiers 2012: 249-252 |
| 2011 |
| 18 |  | Naoki Fujieda,
Kenji Kise:
A Partitioning Method of Cooperative Caching with Hit Frequency Counters for Many-Core Processors.
ICNC 2011: 160-165 |
| 17 |  | Tomoyuki Nagatsuka,
Yoshito Sakaguchi,
Takayuki Matsumura,
Kenji Kise:
CoreSymphony: an efficient reconfigurable multi-core architecture.
SIGARCH Computer Architecture News 39(4): 32-37 (2011) |
| 16 |  | Shinya Takamaeda-Yamazaki,
Ryosuke Sasakawa,
Yoshito Sakaguchi,
Kenji Kise:
An FPGA-based scalable simulation accelerator for tile architectures.
SIGARCH Computer Architecture News 39(4): 38-43 (2011) |
| 2010 |
| 15 |  | Shinya Takamaeda,
Shimpei Sato,
Takefumi Miyoshi,
Kenji Kise:
Smart Core System for Dependable Many-Core Processor with Multifunction Routers.
ICNC 2010: 133-139 |
| 14 |  | Shintaro Sano,
Masahiro Sano,
Shimpei Sato,
Takefumi Miyoshi,
Kenji Kise:
Pattern-Based Systematic Task Mapping for Many-Core Processors.
ICNC 2010: 173-178 |
| 13 |  | Takefumi Miyoshi,
Kenji Kise,
Hidetsugu Irie,
Tsutomu Yoshinaga:
CODIE: Continuation-Based Overlapping Data-Transfers with Instruction Execution.
ICNC 2010: 71-77 |
| 2009 |
| 12 |  | Koh Uehara,
Shimpei Sato,
Takefumi Miyoshi,
Kenji Kise:
A Study of an Infrastructure for Research and Development of Many-Core Processors.
PDCAT 2009: 414-419 |
| 11 |  | Yosuke Mori,
Kenji Kise:
The Cache-Core Architecture to Enhance the Memory Performance on Multi-Core Processors.
PDCAT 2009: 445-450 |
| 2007 |
| 10 |  | Kenji Kise,
Toshinori Sato,
Hironori Nakajo:
Introduction.
SIGARCH Computer Architecture News 35(5): 1-2 (2007) |
| 2006 |
| 9 |  | Satoshi Ohshima,
Kenji Kise,
Takahiro Katagiri,
Toshitsugu Yuba:
Parallel Processing of Matrix Multiplication in a CPU and GPU Heterogeneous Environment.
VECPAR 2006: 305-318 |
| 8 |  | Takahiro Katagiri,
Kenji Kise,
Hiroki Honda,
Toshitsugu Yuba:
ABCLibScript: a directive to support specification of an auto-tuning facility for numerical software.
Parallel Computing 32(1): 92-112 (2006) |
| 7 |  | Takahiro Katagiri,
Kenji Kise,
Hiroki Honda,
Toshitsugu Yuba:
ABCLib_DRSSED: A parallel eigensolver with an auto-tuning facility.
Parallel Computing 32(3): 231-250 (2006) |
| 2005 |
| 6 |  | Kenji Kise,
Takahiro Katagiri,
Hiroki Honda,
Toshitsugu Yuba:
Evaluation of the Acknowledgment Reduction in a Software-DSM System.
PPAM 2005: 17-25 |
| 5 |  | Sanya Tangpongprasit,
Takahiro Katagiri,
Kenji Kise,
Hiroki Honda,
Toshitsugu Yuba:
A time-to-live based reservation algorithm on fully decentralized resource discovery in Grid computing.
Parallel Computing 31(6): 529-543 (2005) |
| 2004 |
| 4 |  | Takahiro Katagiri,
Kenji Kise,
Hiroki Honda,
Toshitsugu Yuba:
Effect of auto-tuning with user's knowledge for numerical software.
Conf. Computing Frontiers 2004: 12-25 |
| 2003 |
| 3 |  | Kenji Kise,
Hiroki Honda,
Toshitsugu Yuba:
SimAlpha Version 1.0: Simple and Readable Alpha Processor Simulator.
Asia-Pacific Computer Systems Architecture Conference 2003: 122-136 |
| 2 |  | Takahiro Katagiri,
Kenji Kise,
Hiroaki Honda,
Toshitsugu Yuba:
FIBER: A Generalized Framework for Auto-tuning Software.
ISHPC 2003: 146-159 |
| 2002 |
| 1 |  | Ryo Takata,
Kenji Kise,
Hiroki Honda,
Toshitsugu Yuba:
DEM-1: A Particle Simulation Machine for Efficient Short-Range Interaction Computations.
IPDPS 2002 |