 | 2011 |
|---|
| 4 |       | Young San Shin,
Jae-Kyung Wee,
Jong-Chan Ha,
Ji-Hoon Lim,
Yong-Ju Kim,
Young-Sang Son:
A Seamless-Controlled Digital PLL Using Dual Loops for High Speed SoCs.
Journal of Circuits, Systems, and Computers 20(4): 741-756 (2011) |
| 2008 |
|---|
| 3 | | Won-Young Jung,
Hyungon Kim,
Yong-Ju Kim,
Jae-Kyung Wee:
Novel Method of Interconnect Worstcase Establishment with Statistically-Based Approaches.
IEICE Transactions 91-A(4): 1177-1184 (2008) |
| 2007 |
|---|
| 2 | | Ji-Hoon Lim,
Jong-Chan Ha,
Won-Young Jung,
Yong-Ju Kim,
Jae-Kyung Wee:
A Novel High-Speed and Low-Voltage CMOS Level-Up/Down Shifter Design for Multiple-Power and Multiple-Clock Domain Chips.
IEICE Transactions 90-C(3): 644-648 (2007) |
| 2006 |
|---|
| 1 | | Yong-Ju Kim,
Won-Young Jung,
Jae-Kyung Wee:
Fast and Accurate Power Bus Designer for Multi-Layers High-Speed Digital Boards.
IEICE Transactions 89-C(7): 1097-1105 (2006) |
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