 | 2010 |
|---|
| 8 |       | Jeong-Gun Lee,
Wook Shin,
Suk-Jin Kim,
Eun-Gu Jung:
A Performance/Energy Analysis and Optimization of Multi-Core Architectures with Voltage Scaling Techniques.
IEICE Transactions 93-A(6): 1215-1225 (2010) |
| 2006 |
|---|
| 7 | | Kyoung-Sik Im,
Jae-Hyok Ko,
Suk-Jin Kim,
Chan-Hee Jeon,
Chang-Su Kim,
Ki-Tae Lee,
Han-Gu Kim,
Il-Hun Son:
Novel ESD strategy for high voltage non-volatile programming pin application.
Microelectronics Reliability 46(9-11): 1664-1668 (2006) |
| 2005 |
|---|
| 6 | | Jeong-Gun Lee,
Suk-Jin Kim,
Jeong-A. Lee,
Kiseon Kim:
A Low Latency Asynchronous FIFO Combining a Wave Pipeline with a Handshake Scheme.
IEICE Transactions 88-A(4): 1031-1037 (2005) |
| 5 | | Suk-Jin Kim,
Jeong-Gun Lee,
Kiseon Kim:
Low Latency Four-Flop Synchronizer with the Handshake Interface.
IEICE Transactions 88-D(7): 1460-1463 (2005) |
| 4 | | Jeong-Gun Lee,
Jeong-A. Lee,
Suk-Jin Kim,
Kiseon Kim:
Design of a Mutated Adder and Its Optimization Using ILP Formulation.
IEICE Transactions 88-D(7): 1506-1508 (2005) |
| 2003 |
|---|
| 3 | | Joep L. W. Kessels,
Ad M. G. Peeters,
Suk-Jin Kim:
Bridging Clock Domains by Synchronizing the Mice in the Mousetrap.
PATMOS 2003: 141-150 |
| 2 | | Joep L. W. Kessels,
Ad M. G. Peeters,
Paul Wielage,
Suk-Jin Kim:
Clock synchronization through handshake signalling.
Microprocessors and Microsystems 27(9): 447-460 (2003) |
| 2002 |
|---|
| 1 | | Joep L. W. Kessels,
Suk-Jin Kim,
Ad M. G. Peeters,
Paul Wielage:
Clock Synchronization through Handshake Signalling.
ASYNC 2002: 59-68 |
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