Jae-Joon Kim

	2011
15		Sang Phill Park, Soo Youn Kim, Dongsoo Lee, Jae-Joon Kim, W. Paul Griffin, Kaushik Roy: Column-selection-enabled 8T SRAM array with ~1R/1W multi-port operation for DVFS-enabled processors. ISLPED 2011: 303-308
14		Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang: SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage. IEEE Trans. VLSI Syst. 19(1): 24-32 (2011)
13		Ik Joon Chang, Jae-Joon Kim, Keejong Kim, Kaushik Roy: Robust Level Converter for Sub-Threshold/Super-Threshold Operation: 100 mV to 2.5 V. IEEE Trans. VLSI Syst. 19(8): 1429-1437 (2011)
	2010
12		Jae-Joon Kim, Rahul M. Rao, Keunwoo Kim: Technology-circuit co-design of asymmetric SRAM cells for read stability improvement. CICC 2010: 1-4
11		Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy: Self-Repairing SRAM Using On-Chip Detection and Compensation. IEEE Trans. VLSI Syst. 18(1): 75-84 (2010)
	2009
10		Aditya Bansal, Rahul M. Rao, Jae-Joon Kim, Sufi Zafar, James H. Stathis, Ching-Te Chuang: Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability. Microelectronics Reliability 49(6): 642-649 (2009)
	2008
9		Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang: Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies. ISCAS 2008: 384-387
8		Aditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy: Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. VLSI Design 2008: 125-130
7		Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown: On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit. VLSI Design 2008: 143-149
6		Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy: Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry. VTS 2008: 101-106
	2007
5		Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy: Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices. Microelectronics Journal 38(8-9): 931-941 (2007)
	2006
4		Ik Joon Chang, Jae-Joon Kim, Kaushik Roy: Robust level converter design for sub-threshold logic. ISLPED 2006: 14-19
	2005
3		Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy: Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. ISQED 2005: 410-415
2		Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy: A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations. IEEE Trans. VLSI Syst. 13(3): 349-357 (2005)
	2003
1		Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy: A forward body-biased low-leakage SRAM cache: device and architecture considerations. ISLPED 2003: 6-9

Coauthor Index

1	Aditya Bansal	[8] [10]
2	Richard B. Brown	[7]
3	Ik Joon Chang	[4] [13]
4	Ching-Te Chuang	[3] [5] [6] [7] [8] [9] [10] [11] [14]
5	Amlan Ghosh	[7]
6	W. Paul Griffin	[15]
7	Rajiv V. Joshi	[3] [5]
8	Chris H. Kim	[1] [2]
9	Keejong Kim	[13]
10	Keunwoo Kim	[3] [5] [8] [12]
11	Soo Youn Kim	[15]
12	Dongsoo Lee	[15]
13	Shih-Hsien Lo	[3] [5]
14	Niladri Narayan Mojumder	[6] [11]
15	Saibal Mukhopadhyay	[1] [2] [3] [5] [6] [8] [9] [11] [14]
16	Sang Phill Park	[15]
17	Rahul M. Rao	[7] [9] [10] [12] [14]
18	Kaushik Roy	[1] [2] [3] [4] [5] [6] [8] [11] [13] [15]
19	James H. Stathis	[10]
20	Sufi Zafar	[10]

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