Hyungwon Kim

	2001
5		Hyungwon Kim, John P. Hayes: Delay fault testing of IP-based designs via symbolic path modeling. IEEE Trans. VLSI Syst. 9(5): 661-678 (2001)
4		Hyungwon Kim, John P. Hayes: Realization-independent ATPG for designs with unimplemented blocks. IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 290-306 (2001)
	1999
3		Hyungwon Kim, John P. Hayes: Delay fault testing of IP-based designs via symbolic path modeling. ITC 1999: 1045-1054
2		Hyungwon Kim, John P. Hayes: Delay Fault Testing of Designs with Embedded IP Cores. VTS 1999: 160-167
	1998
1		Hyungwon Kim, John P. Hayes: High-coverage ATPG for datapath circuits with unimplemented blocks. ITC 1998: 577-586

Coauthor Index

1

John P. Hayes

[1] [2] [3] [4] [5]

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