 | 2011 |
| 9 |  | Katsuyuki Ikeuchi,
Hideki Kusamitsu,
Mutsuo Daito,
Gil-Su Kim,
Makoto Takamiya,
Takayasu Sakurai:
1 Gb/s, 50 µm × 50 µm Pads on Board Wireless Connector Based on Track-and-Charge Scheme Allowing Contacted Signaling.
IEICE Transactions 94-C(6): 992-998 (2011) |
| 8 |  | Mutsuo Daito,
Yoshiro Nakata,
Satoshi Sasaki,
Hiroyuki Gomyo,
Hideki Kusamitsu,
Yoshio Komoto,
Kunihiko Iizuka,
Katsuyuki Ikeuchi,
Gil-Su Kim,
Makoto Takamiya,
Takayasu Sakurai:
Capacitively Coupled Non-Contact Probing Circuits for Membrane-Based Wafer-Level Simultaneous Testing.
J. Solid-State Circuits 46(10): 2386-2395 (2011) |
| 2010 |
| 7 |  | Gil-Su Kim,
Katsuyuki Ikeuchi,
Mutsuo Daito,
Makoto Takamiya,
Takayasu Sakurai:
A high-speed, low-power capacitive-coupling transceiver for wireless wafer-level testing systems.
3DIC 2010: 1-4 |
| 6 |  | Mutsuo Daito,
Yoshiro Nakata,
Satoshi Sasaki,
Hiroyuki Gomyo,
Hideki Kusamitsu,
Yoshio Komoto,
Kunihiko Iizuka,
Katsuyuki Ikeuchi,
Gil-Su Kim,
Makoto Takamiya,
Takayasu Sakurai:
Capacitively coupled non-contact probing circuits for membrane-based wafer-level simultaneous testing.
ISSCC 2010: 144-145 |
| 2009 |
| 5 |  | Gil-Su Kim,
Makoto Takamiya,
Takayasu Sakurai:
A capacitive coupling interface with high sensitivity for wireless wafer testing.
3DIC 2009: 1-5 |
| 4 |  | Jabeom Koo,
Gil-Su Kim,
Junyoung Song,
Kwan-Weon Kim,
Young-Jung Choi,
Chulwoo Kim:
Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application.
CICC 2009: 717-720 |
| 3 |  | Gil-Su Kim,
Makoto Takamiya,
Takayasu Sakurai:
A 25-mV-Sensitivity 2-Gb/s Optimum-Logic-Threshold Capacitive-Coupling Receiver for Wireless Wafer Probing Systems.
IEEE Trans. on Circuits and Systems 56-II(9): 709-713 (2009) |
| 2007 |
| 2 |  | Ji-Yong Jeong,
Gil-Su Kim,
Seung-Hoon Oh,
Kyu-Young Kim,
Soo-Won Kim:
The Wide Input Range Automatic-Threshold Control Circuit for High Definition Digital Audio Interface.
ISCAS 2007: 2558-2561 |
| 2006 |
| 1 |  | Ji-Yong Jeong,
Gil-Su Kim,
Jong-Pil Son,
Woo-Jin Rim,
Soo-Won Kim:
Body Bias Generator for Leakage Power Reduction of Low-Voltage Digital Logic Circuits.
PATMOS 2006: 350-359 |