Chris H. Kim

	2012
60		Tae-Hyoung Kim, Wei Zhang, Chris H. Kim: An SRAM Reliability Test Macro for Fully Automated Statistical Measurements of ${\rm V} _{\rm MIN}$ Degradation. IEEE Trans. on Circuits and Systems 59-I(3): 584-593 (2012)
59		Ki Chul Chun, Pulkit Jain, Tae-Ho Kim, Chris H. Kim: A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches. J. Solid-State Circuits 47(2): 547-559 (2012)
	2011
58		Pingqiang Zhou, Dong Jiao, Chris H. Kim, Sachin S. Sapatnekar: Exploration of on-chip switched-capacitor DC-DC converter for multicore processors using a distributed power delivery network. CICC 2011: 1-4
57		Dong Jiao, Chris H. Kim: A programmable adaptive phase-shifting PLL for clock data compensation under resonant supply noise. ISSCC 2011: 272-274
56		Wei Zhang, Mingjing Ha, Daniele Braga, Michael J. Renn, C. Daniel Frisbie, Chris H. Kim: A 1V printed organic DRAM cell based on ion-gel gated transistors with a sub-10nW-per-cell Refresh Power. ISSCC 2011: 326-328
55		Ki Chul Chun, Wei Zhang, Pulkit Jain, Chris H. Kim: A 700MHz 2T1C embedded DRAM macro in a generic logic process with no boosted supplies. ISSCC 2011: 506-507
54		Chris H. Kim, Leland Chang: Guest editors' introduction: Nanoscale Memories Pose Unique Challenges. IEEE Design & Test of Computers 28(1): 6-8 (2011)
53		Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar: Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits. IEEE Trans. VLSI Syst. 19(4): 603-614 (2011)
52		John Keane, S. Venkatraman, Paulo F. Butzen, Chris H. Kim: An Array-Based Test Circuit for Fully Automated Gate Dielectric Breakdown Characterization. IEEE Trans. VLSI Syst. 19(5): 787-795 (2011)
51		John Keane, Wei Zhang, Chris H. Kim: An Array-Based Odometer System for Statistically Significant Circuit Aging Characterization. J. Solid-State Circuits 46(10): 2374-2385 (2011)
50		Ki Chul Chun, Pulkit Jain, Jung Hwa Lee, Chris H. Kim: A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches. J. Solid-State Circuits 46(6): 1495-1505 (2011)
	2010
49		Vojin G. Oklobdzija, Barry Pangle, Naehyuck Chang, Naresh R. Shanbhag, Chris H. Kim: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010 ACM 2010
48		Ki Chul Chun, Pulkit Jain, Chris H. Kim: Logic-compatible embedded DRAM design for memory intensive low power systems. ISCAS 2010: 277-280
47		Wei Zhang, Ki Chul Chun, Chris H. Kim: Variation aware performance analysis of gain cell embedded DRAMs. ISLPED 2010: 19-24
46		John Keane, Tae-Hyoung Kim, Chris H. Kim: An On-Chip NBTI Sensor for Measuring pMOS Threshold Voltage Degradation. IEEE Trans. VLSI Syst. 18(6): 947-956 (2010)
45		Dong Jiao, Jie Gu, Chris H. Kim: Circuit Design and Modeling Techniques for Enhancing the Clock-Data Compensation Effect Under Resonant Supply Noise. J. Solid-State Circuits 45(10): 2130-2141 (2010)
44		John Keane, Xiaofei Wang, Devin Persaud, Chris H. Kim: An All-In-One Silicon Odometer for Separately Monitoring HCI, BTI, and TDDB. J. Solid-State Circuits 45(4): 817-829 (2010)
43		John Keane, Tae-Hyoung Kim, Xiaofei Wang, Chris H. Kim: On-chip reliability monitors for measuring circuit degradation. Microelectronics Reliability 50(8): 1039-1053 (2010)
	2009
42		Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar: Adaptive techniques for overcoming performance degradation due to aging in digital circuits. ASP-DAC 2009: 284-289
41		Tae-Hyoung Kim, Wei Zhang, Chris H. Kim: An SRAM reliability test macro for fully-automated statistical measurements of Vmin degradation. CICC 2009: 231-234
40		Dong Jiao, Jie Gu, Chris H. Kim: Circuit techniques for enhancing the clock data compensation effect under resonant supply noise. CICC 2009: 29-32
39		Ki Chul Chun, Pulkit Jain, Chris H. Kim: A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM. ISLPED 2009: 119-120
38		Jie Gu, John Keane, Chris H. Kim: Fuer Chris H. Kim 2 Eintraege in Db, Chris H. Kim und Chris Kim. Identisch. Siehe EE-Links: Univ. of Minnesota. Modeling, Analysis, and Application of Leakage Induced Damping Effect for Power Supply Integrity. IEEE Trans. VLSI Syst. 17(1): 128-136 (2009)
37		Jie Gu, Ramesh Harjani, Chris H. Kim: Design and Implementation of Active Decoupling Capacitor Circuits for Power Supply Regulation in Digital ICs. IEEE Trans. VLSI Syst. 17(2): 292-301 (2009)
36		Jie Gu, Hanyong Eom, John Keane, Chris H. Kim: Sleep Transistor Sizing and Adaptive Control for Supply Noise Minimization Considering Resonance. IEEE Trans. VLSI Syst. 17(9): 1203-1211 (2009)
	2008
35		Tae-Hyoung Kim, Jason Liu, John Keane, Chris H. Kim: Circuit techniques for ultra-low power subthreshold SRAMs. ISCAS 2008: 2574-2577
34		Dong Jiao, Jie Gu, Pulkit Jain, Chris H. Kim: Enhancing beneficial jitter using phase-shifted clock distribution. ISLPED 2008: 21-26
33		Pulkit Jain, Tae-Hyoung Kim, John Keane, Chris H. Kim: A multi-story power delivery technique for 3D integrated circuits. ISLPED 2008: 57-62
32		Chris H. Kim: Tutorial 2: Low Voltage Circuit Design Techniques for Sub-32nm Technologies. ISQED 2008: 4
31		Jie Gu, John Keane, Sachin S. Sapatnekar, Chris H. Kim: Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property. IEEE Trans. VLSI Syst. 16(2): 206-209 (2008)
30		Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar: Body Bias Voltage Computations for Process and Temperature Compensation. IEEE Trans. VLSI Syst. 16(3): 249-262 (2008)
29		Jonggab Kil, Jie Gu, Chris H. Kim: A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting. IEEE Trans. VLSI Syst. 16(4): 456-465 (2008)
28		John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim: Stack Sizing for Optimal Current Drivability in Subthreshold Circuits. IEEE Trans. VLSI Syst. 16(5): 598-602 (2008)
	2007
27		Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas: Modeling and estimating leakage current in series-parallel CMOS networks. ACM Great Lakes Symposium on VLSI 2007: 269-274
26		Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar: NBTI-Aware Synthesis of Digital Circuits. DAC 2007: 370-375
25		Jie Gu, Sachin S. Sapatnekar, Chris H. Kim: Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift. DAC 2007: 87-92
24		John Keane, Tae-Hyoung Kim, Chris H. Kim: An on-chip NBTI sensor for measuring PMOS threshold voltage degradation. ISLPED 2007: 189-194
23		Jie Gu, Hanyong Eom, Chris H. Kim: Sleep transistor sizing and control for resonant supply noise damping. ISLPED 2007: 80-85
22		Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas: Modeling Subthreshold Leakage Current in General Transistor Networks. ISVLSI 2007: 512-513
21		Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas: Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates. PATMOS 2007: 474-484
20		Tae-Hyoung Kim, John Keane, Hanyong Eom, Chris H. Kim: Utilizing Reverse Short-Channel Effect for Optimal Subthreshold Circuit Design. IEEE Trans. VLSI Syst. 15(7): 821-829 (2007)
	2006
19		Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar: Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems. ASP-DAC 2006: 559-564
18		John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim: Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing. DAC 2006: 425-428
17		Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar: An analytical model for negative bias temperature instability. ICCAD 2006: 493-496
16		Tae-Hyoung Kim, Hanyong Eom, John Keane, Chris H. Kim: Utilizing reverse short channel effect for optimal subthreshold circuit design. ISLPED 2006: 127-130
15		Jie Gu, John Keane, Chris H. Kim: Modeling and analysis of leakage induced damping effect in low voltage LSIs. ISLPED 2006: 382-387
14		Jonggab Kil, Jie Gu, Chris H. Kim: A high-speed variation-tolerant interconnect technique for sub threshold circuits using capacitive boosting. ISLPED 2006: 67-72
13		Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar: Impact of NBTI on SRAM Read Stability and Design for Reliability. ISQED 2006: 210-218
12		Amit Agarwal, Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy, Chris H. Kim: Leakage Power Analysis and Reduction for Nanoscale Circuits. IEEE Micro 26(2): 68-80 (2006)
11		Chris H. Kim, Kaushik Roy, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar: A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits. IEEE Trans. VLSI Syst. 14(6): 646-649 (2006)
	2005
10		Chris H. Kim, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar, Kaushik Roy: Self Calibrating Circuit Design for Variation Tolerant VLSI Systems. IOLTS 2005: 100-105
9		Jie Gu, Chris H. Kim: Multi-story power delivery for supply noise reduction and low voltage operation. ISLPED 2005: 192-197
8		Keejong Kim, Chris H. Kim, Kaushik Roy: TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique. ISQED 2005: 59-64
7		Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy: A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations. IEEE Trans. VLSI Syst. 13(3): 349-357 (2005)
	2004
6		Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, Kaushik Roy: Leakage in nano-scale technologies: mechanisms, impact and design considerations. DAC 2004: 6-11
5		Hari Ananthan, Chris H. Kim, Kaushik Roy: Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS. ISLPED 2004: 8-13
	2003
4		Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy: A forward body-biased low-leakage SRAM cache: device and architecture considerations. ISLPED 2003: 6-9
3		Saibal Mukhopadhyay, Cassondra Neau, R. T. Cakici, Amit Agarwal, Chris H. Kim, Kaushik Roy: Gate leakage reduction for scaled devices using transistor stacking. IEEE Trans. VLSI Syst. 11(4): 716-730 (2003)
	2002
2		Chris H. Kim, Kaushik Roy: Dynamic VTH Scaling Scheme for Active Leakage Power Reduction. DATE 2002: 163-167
1		Chris H. Kim, Kaushik Roy: Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors. ISLPED 2002: 251-254

Coauthor Index

1	Amit Agarwal	[3] [6] [12]
2	Hari Ananthan	[5]
3	Shekhar Y. Borkar (Shekhar Borkar)	[10] [11]
4	Daniele Braga	[56]
5	Paulo F. Butzen	[21] [22] [27] [52]
6	R. T. Cakici	[3]
7	Leland Chang	[54]
8	Naehyuck Chang	[49]
9	Ki Chul Chun	[39] [47] [48] [50] [55] [59]
10	Hanyong Eom	[16] [18] [20] [23] [28] [36]
11	C. Daniel Frisbie	[56]
12	Jie Gu	[9] [14] [15] [23] [25] [29] [31] [34] [36] [37] [38] [40] [45]
13	Mingjing Ha	[56]
14	Ramesh Harjani	[37]
15	Steven Hsu	[10] [11]
16	Pulkit Jain	[33] [34] [39] [48] [50] [55] [59]
17	Dong Jiao	[34] [40] [45] [57] [58]
18	John Keane	[15] [16] [18] [20] [24] [28] [31] [33] [35] [36] [38] [43] [44] [46] [51] [52]
19	Jonggab Kil	[14] [29]
20	Jae-Joon Kim	[4] [7]
21	Keejong Kim	[8]
22	Tae-Ho Kim	[59]
23	Tae-Hyoung Kim	[16] [18] [20] [24] [28] [33] [35] [41] [43] [46] [60]
24	Ram Krishnamurthy	[10] [11]
25	Sanjay V. Kumar	[13] [17] [19] [26] [30] [42] [53]
26	Jung Hwa Lee	[50]
27	Jason Liu	[35]
28	Saibal Mukhopadhyay	[3] [4] [6] [7] [12]
29	Cassondra Neau	[3]
30	Vojin G. Oklobdzija	[49]
31	Barry Pangle	[49]
32	Devin Persaud	[44]
33	Arijit Raychowdhury	[12]
34	André Inácio Reis	[21] [22] [27]
35	Michael J. Renn	[56]
36	Renato P. Ribas	[21] [22] [27]
37	Kaushik Roy	[1] [2] [3] [4] [5] [6] [7] [8] [10] [11] [12]
38	Sachin S. Sapatnekar	[13] [17] [18] [19] [25] [26] [28] [30] [31] [42] [53] [58]
39	Naresh R. Shanbhag	[49]
40	S. Venkatraman	[52]
41	Xiaofei Wang	[43] [44]
42	Wei Zhang	[41] [47] [51] [55] [56] [60]
43	Pingqiang Zhou	[58]

Colors in the list of coauthors

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