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| 2011 | ||
|---|---|---|
| 38 | Razvan Nane, Sven van Haastregt, Todor Stefanov, Bart Kienhuis, Vlad Mihai Sima, Koen Bertels: IP-XACT extensions for Reconfigurable Computing. ASAP 2011: 215-218 | |
| 37 | Sven van Haastregt, Stephen Neuendorffer, Kees A. Vissers, Bart Kienhuis: High level synthesis for FPGAs applied to a sphere decoder channel preprocessor (abstract only). FPGA 2011: 278 | |
| 36 | Ana Balevic, Bart Kienhuis: A data parallel view on polyhedral process networks. SCOPES 2011: 38-47 | |
| 35 | Ana Balevic, Bart Kienhuis: KPN2GPU: an approach for discovery and exploitation of fine-grain data parallelism in process networks. SIGARCH Computer Architecture News 39(4): 66-71 (2011) | |
| 2010 | ||
| 34 | Sven van Haastregt, Eyal Halm, Bart Kienhuis: Cost modeling and cycle-accurate co-simulation of heterogeneous multiprocessor systems. DATE 2010: 1297-1300 | |
| 33 | Rainer Leupers, Lothar Thiele, Xiaoning Nie, Bart Kienhuis, Matthias Weiss, Tsuyoshi Isshiki: Cool MPSoC programming. DATE 2010: 1488-1493 | |
| 2009 | ||
| 32 | Sven van Haastregt, Bart Kienhuis: Automated synthesis of streaming C applications to process networks in hardware. DATE 2009: 890-893 | |
| 31 | Barbara M. Chapman, Bart Kienhuis, Eduard Ayguadé, François Bodin, Oscar G. Plata, Eric Stotzer: Introduction. Euro-Par 2009: 837-838 | |
| 2008 | ||
| 30 | Bin Jiang, Ed F. Deprettere, Bart Kienhuis: Hierarchical run time deadlock detection in process networks. SiPS 2008: 239-244 | |
| 29 | Steven Derrien, Alexandru Turjan, Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere: Deriving efficient control in Process Networks with Compaan/Laura. IJES 3(3): 170-180 (2008) | |
| 2007 | ||
| 28 | Sjoerd Meijer, Bart Kienhuis, Alexandru Turjan, Erwin A. de Kock: Interactive presentation: A process splitting transformation for Kahn process networks. DATE 2007: 1355-1360 | |
| 27 | Sjoerd Meijer, Bart Kienhuis, Johan Walters, David Snuijf: Automatic partitioning and mapping of stream-based applications onto the Intel IXP Network processor. SCOPES 2007: 23-30 | |
| 26 | Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere: Classifying interprocess communication in process network representation of nested-loop programs. ACM Trans. Embedded Comput. Syst. 6(2): (2007) | |
| 25 | Ming-Yung Ko, Claudiu Zissulescu, Sebastian Puthenpurayil, Shuvra S. Bhattacharyya, Bart Kienhuis, Ed F. Deprettere: Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation. IEEE Transactions on Signal Processing 55(6-2): 3126-3138 (2007) | |
| 2005 | ||
| 24 | Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere: Expression Synthesis in Process Networks generated by LAURA. ASAP 2005: 15-21 | |
| 23 | Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere: Communication Synthesis in a multiprocessor environment. FPL 2005: 360-365 | |
| 22 | Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere: Solving Out-of-Order Communication in Kahn Process Networks. VLSI Signal Processing 40(1): 7-18 (2005) | |
| 2004 | ||
| 21 | Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere: A Hierarchical Classification Scheme to Derive Interprocess Communication in Process Networks. ASAP 2004: 282-292 | |
| 20 | Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere: Translating affine nested-loop programs to process networks. CASES 2004: 220-229 | |
| 19 | Todor Stefanov, Claudiu Zissulescu, Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere: System Design Using Kahn Process Networks: The Compaan/Laura Approach. DATE 2004: 340-345 | |
| 18 | Ingrid Verbauwhede, Patrick Schaumont, Christian Piguet, Bart Kienhuis: Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing. DATE 2004: 988-995 | |
| 17 | Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere: Increasing Pipelined IP Core Utilization in Process Networks Using Exploration. FPL 2004: 690-699 | |
| 16 | Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere: An Integer Linear Programming Approach to Classify the Communication in Process Networks. SCOPES 2004: 62-76 | |
| 2003 | ||
| 15 | Alexandru Turjan, Bart Kienhuis: Storage Management in Process Networks using the Lexicographically Maximal Preimage. ASAP 2003: 75-85 | |
| 14 | Claudiu Zissulescu, Todor Stefanov, Bart Kienhuis, Ed F. Deprettere: Laura: Leiden Architecture Research and Exploration Tool. FPL 2003: 911-920 | |
| 13 | Bart Kienhuis, Ed F. Deprettere: Modeling Stream-Based Applications Using the SBF Model of Computation. VLSI Signal Processing 34(3): 291-300 (2003) | |
| 2002 | ||
| 12 | Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere: A Compile Time Based Approach for Solving Out-of-Order Communication in Kahn Process Networks. ASAP 2002: 17-28 | |
| 11 | Todor Stefanov, Bart Kienhuis, Ed F. Deprettere: Algorithmic transformation techniques for efficient exploration of alternative application instances. CODES 2002: 7-12 | |
| 10 | Bart Kienhuis, Ed F. Deprettere, Pieter van der Wolf, Kees A. Vissers: A Methodology to Design Programmable Embedded Systems - The Y-Chart Approach. Embedded Processor Design Challenges 2002: 18-37 | |
| 9 | Ed F. Deprettere, Edwin Rijpkema, Bart Kienhuis: Translating Imperative Affine Nested Loop Programs into Process Networks. Embedded Processor Design Challenges 2002: 89-111 | |
| 8 | Ed F. Deprettere, Bart Kienhuis, Richard L. Walke: Preface. Design Autom. for Emb. Sys. 7(4): 303-305 (2002) | |
| 7 | Tim Harriss, Richard L. Walke, Bart Kienhuis, Ed F. Deprettere: Compilation From Matlab to Process Networks Realized in FPGA. Design Autom. for Emb. Sys. 7(4): 385-403 (2002) | |
| 2000 | ||
| 6 | Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, Bart Kienhuis: High Level Modeling for Parallel Executions of Nested Loop Algorithms. ASAP 2000: 79-91 | |
| 5 | Bart Kienhuis, Edwin Rijpkema, Ed F. Deprettere: Compaan: deriving process networks from Matlab for embedded signal processing architectures. CODES 2000: 13-17 | |
| 4 | Edwin Rijpkema, Ed F. Deprettere, Bart Kienhuis: Deriving Process Networks from Nested Loop Algorithms. Parallel Processing Letters 10(2/3): 165-176 (2000) | |
| 1999 | ||
| 3 | Paul Lieverse, Ed F. Deprettere, Bart Kienhuis, Erwin A. de Kock: A Clustering Approach to Explore Grain-Sizes in the Definition of Processing Elements in Dataflow Architectures. VLSI Signal Processing 22(1): 9-20 (1999) | |
| 1998 | ||
| 2 | Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf: The construction of a retargetable simulator for an architecture template. CODES 1998: 125-129 | |
| 1997 | ||
| 1 | Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf: An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures. ASAP 1997: 338-349 | |
Colors in the list of coauthors
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