 | 2011 |
| 14 |  | Behrooz Abiri,
Ravi Shivnaraine,
Ali Sheikholeslami,
Hirotaka Tamura,
Masaya Kibune:
A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS.
ISSCC 2011: 154-156 |
| 13 |  | Shayan Shahramian,
Clifford Ting,
Ali Sheikholeslami,
Hirotaka Tamura,
Masaya Kibune:
A pattern-guided adaptive equalizer in 65nm CMOS.
ISSCC 2011: 354-356 |
| 12 |  | Behrooz Abiri,
Ali Sheikholeslami,
Hirotaka Tamura,
Masaya Kibune:
A 5Gb/s adaptive DFE for 2x blind ADC-based CDR in 65nm CMOS.
ISSCC 2011: 436-438 |
| 11 |  | Behrooz Abiri,
Ali Sheikholeslami,
Hirotaka Tamura,
Masaya Kibune:
An Adaptation Engine for a 2x Blind ADC-Based CDR in 65 nm CMOS.
J. Solid-State Circuits 46(12): 3140-3149 (2011) |
| 2010 |
| 10 |  | Tina Tahmoureszadeh,
Siamak Sarvari,
Ali Sheikholeslami,
Hirotaka Tamura,
Yasumoto Tomita,
Masaya Kibune:
A combined anti-aliasing filter and 2-tap FFE in 65-nm CMOS for 2× blind 2-;10 Gb/s ADC-based receivers.
CICC 2010: 1-4 |
| 9 |  | Oleksiy Tyshchenko,
Ali Sheikholeslami,
Hirotaka Tamura,
Yasumoto Tomita,
Hisakatsu Yamaguchi,
Masaya Kibune,
Takuji Yamamoto:
A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS.
ISSCC 2010: 166-167 |
| 8 |  | Hisakatsu Yamaguchi,
Hirotaka Tamura,
Yoshiyasu Doi,
Yasumoto Tomita,
Takayuki Hamada,
Masaya Kibune,
Shuhei Ohmoto,
Keita Tateishi,
Oleksiy Tyshchenko,
Ali Sheikholeslami,
Tomokazu Higuchi,
Junji Ogawa,
Tamio Saito,
Hideki Ishida,
Kohtaroh Gotoh:
A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS.
ISSCC 2010: 168-169 |
| 7 |  | Xiaolei Zhu,
Yanfei Chen,
Masaya Kibune,
Yasumoto Tomita,
Takayuki Hamada,
Hirotaka Tamura,
Sanroku Tsukamoto,
Tadahiro Kuroda:
A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology.
IEICE Transactions 93-A(12): 2456-2462 (2010) |
| 6 |  | Yanfei Chen,
Xiaolei Zhu,
Hirotaka Tamura,
Masaya Kibune,
Yasumoto Tomita,
Takayuki Hamada,
Masato Yoshioka,
Kiyoshi Ishikawa,
Takeshi Takayama,
Junji Ogawa,
Sanroku Tsukamoto,
Tadahiro Kuroda:
Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC.
IEICE Transactions 93-C(3): 295-302 (2010) |
| 5 |  | Nikola Nedovic,
Anders Kristensson,
Samir Parikh,
Subodh M. Reddy,
Scott McLeod,
Nestoras Tzartzanis,
Kouichi Kanda,
Takuji Yamamoto,
Satoshi Matsubara,
Masaya Kibune,
Yoshiyasu Doi,
Satoshi Ide,
Yukito Tsunoda,
Tetsuji Yamabana,
Takayuki Shibasaki,
Yasumoto Tomita,
Takayuki Hamada,
Mariko Sugawara,
Tadashi Ikeuchi,
Naoki Kuwata,
Hirotaka Tamura,
Junji Ogawa,
William W. Walker:
A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS.
J. Solid-State Circuits 45(10): 2016-2029 (2010) |
| 4 |  | Oleksiy Tyshchenko,
Ali Sheikholeslami,
Hirotaka Tamura,
Masaya Kibune,
Hisakatsu Yamaguchi,
Junji Ogawa:
A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS.
J. Solid-State Circuits 45(6): 1091-1098 (2010) |
| 2009 |
| 3 |  | Yanfei Chen,
Xiaolei Zhu,
Hirotaka Tamura,
Masaya Kibune,
Yasumoto Tomita,
Takayuki Hamada,
Masato Yoshioka,
Kiyoshi Ishikawa,
Takeshi Takayama,
Junji Ogawa,
Sanroku Tsukamoto,
Tadahiro Kuroda:
Split capacitor DAC mismatch calibration in successive approximation ADC.
CICC 2009: 279-282 |
| 2 |  | Kouichi Kanda,
Hirotaka Tamura,
Takuji Yamamoto,
Satoshi Matsubara,
Masaya Kibune,
Yoshiyasu Doi,
Takayuki Shibasaki,
Nestoras Tzartzanis,
Anders Kristensson,
Samir Parikh,
Satoshi Ide,
Yukito Tsunoda,
Tetsuji Yamabana,
Mariko Sugawara,
Naoki Kuwata,
Tadashi Ikeuchi,
Junji Ogawa,
William W. Walker:
A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS.
ISSCC 2009: 360-361 |
| 2006 |
| 1 |  | Hirotaka Tamura,
Masaya Kibune,
Hisakatsu Yamaguchi,
Kouichi Kanda,
Kohtaroh Gotoh,
Hideki Ishida,
Junji Ogawa:
Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies.
IEICE Transactions 89-C(3): 300-313 (2006) |