 | 2010 |
| 20 |  | Jim O'Reilly,
Ajay Khoche,
Ernst Wahl,
Bruce R. Parnas:
STIL P1450.4: A standard for test flow specification.
ITC 2010: 506-515 |
| 2009 |
| 19 |  | Ajay Khoche,
Jay Katz,
Sauro Landini,
Kochen Liao,
Neetu Agrawal,
Glenn Plowman,
Song-lin Zuo,
Liyang Lai,
John Rowe,
Thomas Zanon:
STDF Memory Fail Datalog Standard.
VTS 2009: 209-214 |
| 2008 |
| 18 |  | Ajay Khoche,
Phil Burlison,
John Rowe,
Glenn Plowman:
A Tutorial on STDF Fail Datalog Standard.
ITC 2008: 1-10 |
| 2006 |
| 17 |  | Ajay Khoche,
Domenico Chindamo,
Michael Braun,
Martin Fischer:
Selective and Accurate Fail Data Capture in Compression Environment for Volume Diagnostics.
ITC 2006: 1-10 |
| 16 |  | Ajay Khoche:
Session Abstract.
VTS 2006: 152-153 |
| 15 |  | Ajay Khoche,
Peter Muhmenthaler:
Session Abstract.
VTS 2006: 288-289 |
| 14 |  | Ajay Khoche,
Mike Rodgers,
Pete O'Neil:
Session Abstract.
VTS 2006: 426 |
| 13 |  | Ajay Khoche:
Panel Summaries: Real-Time Volume Diagnostics--Requirements and Challenges.
IEEE Design & Test of Computers 23(4): 315 (2006) |
| 2003 |
| 12 |  | Erik H. Volkerink,
Ajay Khoche,
Jochen Rivoir,
Klaus D. Hilliges:
Modern Test Techniques: Tradeoffs, Synergies, and Scalable Benefits.
J. Electronic Testing 19(2): 125-135 (2003) |
| 2002 |
| 11 |  | Erik H. Volkerink,
Ajay Khoche,
Subhasish Mitra:
Packet-Based Input Test Data Compression Techniques.
ITC 2002: 154-163 |
| 10 |  | Erik H. Volkerink,
Ajay Khoche,
Jochen Rivoir,
Klaus D. Hilliges:
Test Economics for Multi-site Test with Modern Cost Reduction Techniques.
VTS 2002: 411-416 |
| 9 |  | Ajay Khoche,
Erik H. Volkerink,
Jochen Rivoir,
Subhasish Mitra:
Test Vector Compression Using EDA-ATE Synergies.
VTS 2002: 97-102 |
| 2001 |
| 8 |  | Erik H. Volkerink,
Ajay Khoche,
Linda A. Kamas,
Jochen Rivoir,
Hans G. Kerkhoff:
Tackling test trade-offs from design, manufacturing to market using economic modeling.
ITC 2001: 1098-1107 |
| 7 |  | Ajay Khoche,
Rohit Kapur,
David Armstrong,
Thomas W. Williams,
Mick Tegethoff,
Jochen Rivoir:
A new methodology for improved tester utilization.
ITC 2001: 916-923 |
| 1997 |
| 6 |  | Ajay Khoche,
Erik Brunvand:
ACT: A DFT Tool for Self-Timed Circuits.
ITC 1997: 829-837 |
| 5 |  | Ajay Khoche,
Erik Brunvand:
Critical hazard free test generation for asynchronous circuits.
VTS 1997: 203-209 |
| 1995 |
| 4 |  | Ajay Khoche,
Erik Brunvand:
Testing self-timed circuits using partial scan.
ASYNC 1995: 160-169 |
| 3 |  | Sandeep Pagey,
Ajay Khoche,
Erik Brunvand:
DFT for fast testing of self-timed control circuits.
Asian Test Symposium 1995: 382-386 |
| 2 |  | Ajay Khoche,
Erik Brunvand:
A partial scan methodology for testing self-timed circuits.
VTS 1995: 283-289 |
| 1992 |
| 1 |  | Ajay Khoche,
Sunil D. Sherlekar,
G. Venkatesh,
Raja Venkateswaran:
A Behavioral Fault Simulator for Ideal.
IEEE Design & Test of Computers 9(4): 14-21 (1992) |