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| 2012 | ||
|---|---|---|
| 35 | Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep Kulkarni, Vivek De, Dimiter Avresky: Design for test and reliability in ultimate CMOS. DATE 2012: 677-682 | |
| 34 | Jaydeep Kulkarni, Bibiche M. Geuskens, Tanay Karnik, Muhammad M. Khellah, James Tschanz, Vivek De: Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM. ISSCC 2012: 234-236 | |
| 2011 | ||
| 33 | Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek K. De: All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control. IEEE Trans. on Circuits and Systems 58-I(9): 2017-2025 (2011) | |
| 32 | Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek K. De: A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance. J. Solid-State Circuits 46(1): 194-208 (2011) | |
| 31 | Arijit Raychowdhury, Bibiche M. Geuskens, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Tanay Karnik, Muhammad M. Khellah, Vivek K. De: Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays. J. Solid-State Circuits 46(4): 797-805 (2011) | |
| 2010 | ||
| 30 | James Tschanz, Keith A. Bowman, Muhammad M. Khellah, Chris Wilkerson, Bibiche M. Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De: Resilient design in scaled CMOS for energy efficiency. ASP-DAC 2010: 625 | |
| 29 | Keith A. Bowman, Carlos Tokunaga, James Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek De: Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency. CICC 2010: 1-4 | |
| 28 | Bibiche M. Geuskens, Muhammad M. Khellah, Jaydeep Kulkarni, Tanay Karnik, Vivek De: Opportunities for PMOS read and write ports in low voltage dual-port 8T bit cell arrays. CICC 2010: 1-4 | |
| 27 | Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De: Resilient microprocessor design for high performance & energy efficiency. ISLPED 2010: 355-356 | |
| 26 | James Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De: A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance. ISSCC 2010: 282-283 | |
| 25 | Arijit Raychowdhury, Bibiche M. Geuskens, Jaydeep Kulkarni, James Tschanz, Keith A. Bowman, Tanay Karnik, Shih-Lien Lu, Vivek De, Muhammad M. Khellah: PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction. ISSCC 2010: 352-353 | |
| 24 | Dinesh Somasekhar, Balaji Srinivasan, Gunjan Pandya, Fatih Hamzaoglu, Muhammad M. Khellah, Tanay Karnik, Kevin Zhang: Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process. J. Solid-State Circuits 45(4): 751-758 (2010) | |
| 2009 | ||
| 23 | Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad M. Khellah, Shih-Lien Lu: Trading Off Cache Capacity for Low-Voltage Operation. IEEE Micro 29(1): 96-103 (2009) | |
| 22 | Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De: SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus. IEEE Trans. on Circuits and Systems 56-I(2): 384-394 (2009) | |
| 21 | Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De: Serial-Link Bus: A Low-Power On-Chip Bus Architecture. IEEE Trans. on Circuits and Systems 56-I(9): 2020-2032 (2009) | |
| 20 | DiaaEldin Khalil, Muhammad M. Khellah, Nam-Sung Kim, Yehea I. Ismail, Tanay Karnik, Vivek De: SRAM dynamic stability estimation using MPFP and its applications. Microelectronics Journal 40(11): 1523-1530 (2009) | |
| 2008 | ||
| 19 | Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad M. Khellah, Shih-Lien Lu: Trading off Cache Capacity for Reliability to Enable Low Voltage Operation. ISCA 2008: 203-214 | |
| 18 | DiaaEldin Khalil, Yehea I. Ismail, Muhammad M. Khellah, Tanay Karnik, Vivek De: Analytical Model for the Propagation Delay of Through Silicon Vias. ISQED 2008: 553-556 | |
| 17 | D. E. Khalil, Muhammad M. Khellah, Nam-Sung Kim, Yehea I. Ismail, Tanay Karnik, Vivek K. De: Accurate Estimation of SRAM Dynamic Stability. IEEE Trans. VLSI Syst. 16(12): 1639-1647 (2008) | |
| 16 | Maged Ghoneima, Muhammad M. Khellah, James Tschanz, Yibin Ye, Nasser Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail, Vivek K. De: Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses. IEEE Trans. on Circuits and Systems 55-I(7): 1904-1910 (2008) | |
| 2007 | ||
| 15 | Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm: Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling. IEEE Trans. VLSI Syst. 15(7): 746-757 (2007) | |
| 14 | Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek K. De: Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme. VLSI Design 2007: (2007) | |
| 2006 | ||
| 13 | Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Vivek De: Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches. ISCAS 2006 | |
| 12 | Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De: Reducing the data switching activity of serialized datastreams. ISCAS 2006 | |
| 11 | Keith A. Bowman, James Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De: Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance. ISLPED 2006: 79-84 | |
| 10 | Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De: Reducing the Data Switching Activity on Serial Link Buses. ISQED 2006: 425-432 | |
| 9 | Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De: Formal derivation of optimal active shielding for low-power on-chip buses. IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 821-836 (2006) | |
| 2005 | ||
| 8 | Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm: Variations-aware low-power design with voltage scaling. DAC 2005: 529-534 | |
| 7 | Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De: Serial-link bus: a low-power on-chip bus architecture. ICCAD 2005: 541-546 | |
| 6 | Muhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Nasser Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail: A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors. ICCD 2005: 253-257 | |
| 5 | Yehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Vivek De: Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses. ISCAS (1) 2005: 592-595 | |
| 2001 | ||
| 4 | Muhammad M. Khellah, Mohamed I. Elmasry: A low-power high-performance current-mode multiport SRAM. IEEE Trans. VLSI Syst. 9(5): 590-598 (2001) | |
| 1998 | ||
| 3 | A. M. Fahim, Muhammad M. Khellah, Mohamed I. Elmasry: A Low-Power High-Performance Embedded SRAM Macrocell. Great Lakes Symposium on VLSI 1998: 13-17 | |
| 2 | Muhammad M. Khellah, Mohamed I. Elmasry: Effective Capacitance Macro-Modelling for Architectural-Level Power Estimation. Great Lakes Symposium on VLSI 1998: 414-419 | |
| 1996 | ||
| 1 | Stephen Dean Brown, Muhammad M. Khellah, Zvonko G. Vranesic: Minimizing FPGA Interconnect Delays. IEEE Design & Test of Computers 13(4): 16-23 (1996) | |
Colors in the list of coauthors
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