Sunil P. Khatri

	2012
120		Bhavitavya Bhadviya, Ayan Mandal, Sunil P. Khatri: Alleviating NBTI-induced failure in off-chip output drivers. ACM Great Lakes Symposium on VLSI 2012: 295-298
119		Pey-Chang Kent Lin, Ayan Mandal, Sunil P. Khatri: Boolean satisfiability using noise based logic. DAC 2012: 1260-1261
118		Pey-Chang Kent Lin, Sunil P. Khatri: Application of logic synthesis to the understanding and cure of genetic diseases. DAC 2012: 734-740
117		Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra: A fast, source-synchronous ring-based network-on-chip design. DATE 2012: 1489-1494
	2011
116		Pey-Chang Kent Lin, Alex Ivanov, Bradley Johnson, Sunil P. Khatri: A novel cryptographic key exchange scheme using resistors. ICCD 2011: 451-452
115		Ayan Mandal, Nikhil Jayakumar, Kalyana C. Bollapalli, Sunil P. Khatri, Rabi N. Mahapatra: An Automated Approach for Minimum Jitter Buffered H-Tree Construction. VLSI Design 2011: 76-81
114		Ayan Mandal, Vinay Karkala, Sunil P. Khatri, Rabi N. Mahapatra: Interconnected Tile Standing Wave Resonant Oscillator Based Clock Distribution Circuits. VLSI Design 2011: 82-87
113		Laszlo B. Kish, Sunil P. Khatri, Sergey M. Bezrukov, Ferdinand Peper, Zoltan Gingl, Tamás Horváth: Noise-based information processing: Noise-based logic and computing: what do we have so far? CoRR abs/1102.2256: (2011)
112		Pey-Chang Kent Lin, Ayan Mandal, Sunil P. Khatri: Boolean Satisfiability using Noise Based Logic CoRR abs/1110.0550: (2011)
111		Didem Zeliha Turker, Sunil P. Khatri, Edgar Sánchez-Sinencio: A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications. IEEE Trans. on Circuits and Systems 58-I(6): 1225-1238 (2011)
110		Laszlo B. Kish, Sunil P. Khatri, Sergey M. Bezrukov, Ferdinand Peper, Zoltan Gingl, Tamás Horváth: Noise-based Deterministic Logic and Computing: a Brief Survey. IJUC 7(1-2): 101-113 (2011)
	2010
109		Kanupriya Gulati, Sunil P. Khatri: Boolean satisfiability on a graphics processor. ACM Great Lakes Symposium on VLSI 2010: 123-126
108		Pey-Chang Kent Lin, Sunil P. Khatri: VLSI implementation of a non-linear feedback shift register for high-speed cryptography applications. ACM Great Lakes Symposium on VLSI 2010: 381-384
107		Kalyana C. Bollapalli, Sunil P. Khatri, Laszlo B. Kish: Implementing digital logic with sinusoidal supplies. DATE 2010: 315-318
106		Navid Abedini, Sunil P. Khatri, Serap A. Savari: A SAT-Based Scheme to Determine Optimal Fix-Free Codes. DCC 2010: 169-178
105		Vinay Karkala, Joseph Wanstrath, Travis Lacour, Sunil P. Khatri: Efficient arithmetic sum-of-product (SOP) based Multiple Constant Multiplication (MCM) for FFT. ICCAD 2010: 735-738
104		Rajesh Kumar, Sunil P. Khatri: An efficient pulse flip-flop based launch-on-shift scan cell. ISCAS 2010: 4105-4108
103		Nikhil Jayakumar, Sunil P. Khatri: A Simultaneous Input Vector Control and Circuit Modification Technique to Reduce Leakage with Zero Delay Penalty. ACM Trans. Design Autom. Electr. Syst. 16(1): 9 (2010)
102		Zoltan Gingl, Sunil P. Khatri, Laszlo B. Kish: Towards brain-inspired computing CoRR abs/1003.3932: (2010)
101		Laszlo B. Kish, Sunil P. Khatri, Ferdinand Peper: Instantaneous noise-based logic CoRR abs/1004.2652: (2010)
100		Laszlo B. Kish, Sunil P. Khatri, Tamás Horváth: Computation using Noise-based Logic: Efficient String Verification over a Slow Communication Channel CoRR abs/1005.1560: (2010)
99		Laszlo B. Kish, Sunil P. Khatri, Sergey M. Bezrukov, Ferdinand Peper, Zoltan Gingl, Tamás Horváth: Noise-based deterministic logic and computing: a brief survey CoRR abs/1007.5282: (2010)
98		Kanupriya Gulati, Sunil P. Khatri: Fault Table Computation on GPUs. J. Electronic Testing 26(2): 195-209 (2010)
	2009
97		Jeff L. Cobb, Kanupriya Gulati, Sunil P. Khatri: Robust window-based multi-node technology-independent logic minimization. ACM Great Lakes Symposium on VLSI 2009: 357-362
96		Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri: Low power and high performance sram design using bank-based selective forward body bias. ACM Great Lakes Symposium on VLSI 2009: 441-444
95		Kanupriya Gulati, Sunil P. Khatri: Accelerating statistical static timing analysis using graphics processing units. ASP-DAC 2009: 260-265
94		Kanupriya Gulati, John F. Croix, Sunil P. Khatri, Rahm Shastry: Fast circuit simulation on graphics processing units. ASP-DAC 2009: 403-408
93		Rajesh Garg, Sunil P. Khatri: Efficient analytical determination of the SEU-induced pulse shape. ASP-DAC 2009: 461-467
92		Kanupriya Gulati, Sunil P. Khatri, Peng Li: Closed-loop modeling of power and temperature profiles of FPGAs. FPGA 2009: 287
91		Kanupriya Gulati, Sunil P. Khatri: Fault table generation using Graphics Processing Units. HLDVT 2009: 60-67
90		Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri: On-chip bidirectional wiring for heavily pipelined systems using network coding. ICCD 2009: 131-136
89		Rajesh Garg, Sunil P. Khatri: 3D simulation and analysis of the radiation tolerance of voltage scaled digital circuit. ICCD 2009: 498-504
88		Rajesh Kumar, Vinay Karkala, Rajesh Garg, Tanuj Jindal, Sunil P. Khatri: A radiation tolerant Phase Locked Loop design for digital electronics. ICCD 2009: 505-510
87		Vinay Karkala, Kalyana C. Bollapalli, Rajesh Garg, Sunil P. Khatri: A PLL design based on a standing wave resonant oscillator. ICCD 2009: 511-516
86		Rajesh Kumar, Kalyana C. Bollapalli, Rajesh Garg, Tarun Soni, Sunil P. Khatri: A robust pulsed flip-flop and its use in enhanced scan design. ICCD 2009: 97-102
85		Srikanth Alaparthi, Kanupriya Gulati, Sunil P. Khatri: Sorting Binary Numbers in Hardware - A Novel Algorithm and its Implementation. ISCAS 2009: 2225-2228
84		Suganth Paul, Rajesh Garg, Sunil P. Khatri, Sheila Vaidya: Design and implementation of a sub-threshold BFSK transmitter. ISQED 2009: 664-672
83		Rajballav Dash, Rajesh Garg, Sunil P. Khatri, Gwan S. Choi: SEU hardened clock regeneration circuits. ISQED 2009: 806-813
82		Kanupriya Gulati, Suganth Paul, Sunil P. Khatri, Srinivas Patil, Abhijit Jas: FPGA-based hardware acceleration for Boolean satisfiability. ACM Trans. Design Autom. Electr. Syst. 14(2): (2009)
81		Suganth Paul, Nikhil Jayakumar, Sunil P. Khatri: A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations. IEEE Trans. VLSI Syst. 17(2): 269-277 (2009)
80		Chunjie Duan, Victor H. Cordero Calle, Sunil P. Khatri: Efficient On-Chip Crosstalk Avoidance CODEC Design. IEEE Trans. VLSI Syst. 17(4): 551-560 (2009)
79		Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan S. Choi: Circuit-Level Design Approaches for Radiation-Hard Digital Electronics. IEEE Trans. VLSI Syst. 17(6): 781-792 (2009)
78		Sasidharan Ekambavanan, Rajesh Garg, Sunil P. Khatri, Krishna R. Narayanan: Encoding Serial Graphical Data for Energy-Delay Product/Energy Minimization. J. Low Power Electronics 5(2): 157-172 (2009)
77		Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri: Selective Forward Body Bias for High Speed and Low Power SRAMs. J. Low Power Electronics 5(2): 185-195 (2009)
	2008
76		Arunprasad Venkatraman, Rajesh Garg, Sunil P. Khatri: A robust, fast pulsed flip-flop design. ACM Great Lakes Symposium on VLSI 2008: 119-122
75		Kanupriya Gulati, Sunil P. Khatri: Improving FPGA routability using network coding. ACM Great Lakes Symposium on VLSI 2008: 147-150
74		Suganth Paul, Rajesh Garg, Sunil P. Khatri: Pipelined network of PLA based circuit design. ACM Great Lakes Symposium on VLSI 2008: 213-218
73		Salman Gopalani, Rajesh Garg, Sunil P. Khatri, Mosong Cheng: A lithography-friendly structured ASIC design approach. ACM Great Lakes Symposium on VLSI 2008: 315-320
72		Kanupriya Gulati, Sunil P. Khatri: Towards acceleration of fault simulation using graphics processing units. DAC 2008: 822-827
71		Rajesh Garg, Charu Nagpal, Sunil P. Khatri: A fast, analytical estimator for the SEU-induced pulse width in combinational designs. DAC 2008: 918-923
70		Chunjie Duan, Chengyu Zhu, Sunil P. Khatri: Forbidden transition free crosstalk avoidance CODEC design. DAC 2008: 986-991
69		Charu Nagpal, Rajesh Garg, Sunil P. Khatri: A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements. DATE 2008: 354-359
68		Chunjie Duan, Sunil P. Khatri: Energy Efficient and High Speed On-Chip Ternary Bus. DATE 2008: 515-518
67		Rajesh Garg, Gagandeep Mallarapu, Sunil P. Khatri: A Single-supply True Voltage Level Shifter. DATE 2008: 979-984
66		Victor H. Cordero Calle, Sunil P. Khatri: Clock Distribution Scheme using Coplanar Transmission Lines. DATE 2008: 985-990
65		Rajesh Garg, Sunil P. Khatri: A novel, highly SEU tolerant digital circuit design approach. ICCD 2008: 14-20
64		Rajesh Garg, Peng Li, Sunil P. Khatri: Modeling dynamic stability of SRAMS in the presence of single event upsets (SEUs). ISCAS 2008: 1788-1791
63		Sabyasachi Das, Sunil P. Khatri: A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters. VLSI Design 2008: 572-579
62		Sabyasachi Das, Sunil P. Khatri: A Timing-Driven Synthesis Technique for Arithmetic Product-of-Sum Expressions. VLSI Design 2008: 635-640
61		Sabyasachi Das, Sunil P. Khatri: An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products. VLSI Design 2008: 653-659
60		Nikhil Saluja, Kanupriya Gulati, Sunil P. Khatri: SAT-based ATPG using multilevel compatible don't-cares. ACM Trans. Design Autom. Electr. Syst. 13(2): (2008)
59		Sabyasachi Das, Sunil P. Khatri: Resource sharing among mutually exclusive sum-of-product blocks for area reduction. ACM Trans. Design Autom. Electr. Syst. 13(3): (2008)
58		Sabyasachi Das, Sunil P. Khatri: A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic. IEEE Trans. VLSI Syst. 16(3): 326-331 (2008)
57		A. Kapoor, Nikhil Jayakumar, Sunil P. Khatri: Dynamically De-Skewable Clock Distribution Methodology. IEEE Trans. VLSI Syst. 16(9): 1220-1229 (2008)
56		Sabyasachi Das, Sunil P. Khatri: A Timing-Driven Approach to Synthesize Fast Barrel Shifters. IEEE Trans. on Circuits and Systems 55-II(1): 31-35 (2008)
55		Kanupriya Gulati, Mandar Waghmode, Sunil P. Khatri, Weiping Shi: Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction. IET Computers & Digital Techniques 2(3): 214-229 (2008)
54		Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri, D. M. H. Walker: A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations. Integration 41(3): 399-412 (2008)
	2007
53		Nikhil Jayakumar, Sunil P. Khatri: An algorithm to minimize leakage through simultaneous input vector control and circuit modification. DATE 2007: 618-623
52		Eugene Goldberg, Kanupriya Gulati, Sunil P. Khatri: Toggle Equivalence Preserving (TEP) Logic Optimization. DSD 2007: 271-279
51		Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri: A Structured ASIC Design Approach Using Pass Transistor Logic. ISCAS 2007: 1787-1790
50		Jeff L. Cobb, Rajesh Garg, Sunil P. Khatri: A methodology for interconnect dimension determination. ISPD 2007: 189-195
49		Nikhil Jayakumar, Sunil P. Khatri: A Predictably Low-Leakage ASIC Design Style. IEEE Trans. VLSI Syst. 15(3): 276-285 (2007)
48		Vijay Nagarajan, Stefan Laendner, Nikhil Jayakumar, Olgica Milenkovic, Sunil P. Khatri: High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems. VLSI Signal Processing 49(1): 185-206 (2007)
	2006
47		Bo Shen, Sunil P. Khatri, Takis Zourntos: Implementation of MOSFET based capacitors for digital applications. ACM Great Lakes Symposium on VLSI 2006: 180-186
46		Rajesh Garg, Mario Sanchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri: A design flow to optimize circuit delay by using standard cells and PLAs. ACM Great Lakes Symposium on VLSI 2006: 217-222
45		Scott J. Campbell, Sunil P. Khatri: Resource and delay efficient matrix multiplication using newer FPGA devices. ACM Great Lakes Symposium on VLSI 2006: 308-311
44		Brock J. LaMeres, Kanupriya Gulati, Sunil P. Khatri: Controlling inductive cross-talk and power in off-chip buses using CODECs. ASP-DAC 2006: 850-855
43		Nikhil Jayakumar, Rajesh Garg, Bruce Gamache, Sunil P. Khatri: A PLA based asynchronous micropipelining approach for subthreshold circuit design. DAC 2006: 419-424
42		Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan Choi: A design approach for radiation-hard digital electronics. DAC 2006: 773-778
41		Brock J. LaMeres, Sunil P. Khatri: Bus stuttering: an encoding technique to reduce inductive noise in off-chip data transmission. DATE 2006: 522-527
40		Nikhil Jayakumar, Sunil P. Khatri, Kanupriya Gulati, Alexander Sprintson: Network coding for routability improvement in VLSI. ICCAD 2006: 820-823
39		Mandar Waghmode, Kanupriya Gulati, Sunil P. Khatri, Weiping Shi: An Efficient, Scalable Hardware Engine for Boolean SATisfiability. ICCD 2006
38		Eric Menendez, Dumezie Maduike, Rajesh Garg, Sunil P. Khatri: CMOS Comparators for High-Speed and Low-Power Applications. ICCD 2006
37		Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri: On the Improvement of Statistical Static Timing Analysis. ICCD 2006
36		Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri: A probabilistic method to determine the minimum leakage vector for combinational designs. ISCAS 2006
35		Chunjie Duan, Sunil P. Khatri: Computing during supply voltage switching in DVS enabled real-time processors. ISCAS 2006
34		Kanupriya Gulati, M. Lovell, Sunil P. Khatri: Efficient don't care computation for hierarchical designs. ISCAS 2006
33		Rajesh Garg, Sunil P. Khatri: Generalized buffering of PTL logic stages using Boolean division. ISCAS 2006
32		Chunjie Duan, Kanupriya Gulati, Sunil P. Khatri: Memory-based crosstalk canceling CODECs for on-chip buses. ISCAS 2006
	2005
31		Van R. Culver, Sunil P. Khatri: A dynamic voltage scaling algorithm for energy reduction in hard real-time systems. ASP-DAC 2005: 842-845
30		Nikhil Jayakumar, Sandeep Dhar, Sunil P. Khatri: A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents. DAC 2005: 43-46
29		Nikhil Jayakumar, Sunil P. Khatri: A variation tolerant subthreshold design approach. DAC 2005: 716-719
28		Brock J. LaMeres, Sunil P. Khatri: Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data Transmission. DATE 2005: 1318-1323
27		Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert: Practical techniques to reduce skew and its variations in buffered clock networks. ICCAD 2005: 592-596
26		Nikhil Jayakumar, Sunil P. Khatri: Minimum Energy Near-threshold Network of PLA based Design. ICCD 2005: 399-404
25		Seraj Ahmad, Nikhil Jayakumar, Vijay Balasubramanian, Edward Hursey, Sunil P. Khatri, Rabi N. Mahapatra: X-Routing using Two Manhattan Route Instances. ICCD 2005: 45-52
24		Brock J. LaMeres, Sunil P. Khatri: Broadband Impedance Matching for Inductive Interconnect in VLSI Packages. ICCD 2005: 683-688
23		Brock J. LaMeres, Sunil P. Khatri: Performance model for inter-chip communication considering inductive cross-talk and cost. ISCAS (4) 2005: 4130-4133
22		Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri: An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs. ISLPED 2005: 111-114
21		Nikhil Saluja, Sunil P. Khatri: Efficient SAT-based combinational ATPG using multi-level don't-cares. ITC 2005: 10
20		Edward Hursey, Nikhil Jayakumar, Sunil P. Khatri: Non-Manhattan Routing Using a Manhattan Router. VLSI Design 2005: 445-450
	2004
19		Nikhil Saluja, Sunil P. Khatri: A robust algorithm for approximate compatible observability don't care (CODC) computation. DAC 2004: 422-427
18		Chunjie Duan, Sunil P. Khatri: Exploiting Crosstalk to Speed up On-Chip Buse. DATE 2004: 778-783
17		Nikhil Jayakumar, Sunil P. Khatri: A metal and via maskset programmable VLSI design methodology using PLAs. ICCAD 2004: 590-594
16		A. Kapoor, Nikhil Jayakumar, Sunil P. Khatri: A novel clock distribution and dynamic de-skewing methodology. ICCAD 2004: 626-631
15		Sunil P. Khatri, Subarnarekha Sinha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: SPFD-based wire removal in standard-cell and network-of-PLA circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1020-1030 (2004)
	2003
14		Nikhil Jayakumar, Sunil P. Khatri: An ASIC design methodology with predictably low leakage, using leakage-immune standard cells. ISLPED 2003: 128-133
	2002
13		Sabyasachi Das, Sunil P. Khatri: An efficient and regular routing methodology for datapath designsusing net regularity extraction. IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 93-101 (2002)
	2001
12		Wilsin Gosti, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli: Addressing the Timing Closure Problem by Integrating Logic Optimization and Placement. ICCAD 2001: 224-231
11		Sabyasachi Das, Sunil P. Khatri: A regularity-driven fast gridless detailed router for high frequency datapath designs. ISPD 2001: 130-135
	2000
10		Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Cross-Talk Immune VLSI Design Using a Network of PLAs Embedded in a Regular Layout Fabric. ICCAD 2000: 412-418
9		Subarnarekha Sinha, Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks. ICCD 2000: 494-503
	1999
8		Sunil P. Khatri, Amit Mehrotra, Robert K. Brayton, Ralph H. J. M. Otten, Alberto L. Sangiovanni-Vincentelli: A Novel VLSI Layout Fabric for Deep Sub-Micron Applications. DAC 1999: 491-496
7		Robert K. Brayton, Sunil P. Khatri: Multi-Valued Logic Synthesis. VLSI Design 1999: 196-105
6		Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Sequential Multi-Valued Network Simplification using Redundancy Removal. VLSI Design 1999: 206-211
	1996
5		Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa: VIS: A System for Verification and Synthesis. CAV 1996: 428-432
4		Sunil P. Khatri, Amit Narayan, Sriram C. Krishnan, Kenneth L. McMillan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Engineering Change in a Non-Deterministic FSM Setting. DAC 1996: 451-456
3		Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa: VIS. FMCAD 1996: 248-256
2		Jawahar Jain, Amit Narayan, C. Coelho, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton, Masahiro Fujita: Decomposition Techniques for Efficient ROBDD Construction. FMCAD 1996: 419-434
1		Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: A study of composition schemes for mixed apply/compose based construction of ROBDDs. VLSI Design 1996: 249-253

Coauthor Index

1	Navid Abedini	[106]
2	Seraj Ahmad	[25]
3	Srikanth Alaparthi	[85]
4	Charles J. Alpert	[27]
5	Adnan Aziz	[3] [5]
6	Vijay Balasubramanian	[25]
7	Sergey M. Bezrukov	[99] [110] [113]
8	Bhavitavya Bhadviya	[120]
9	Kalyana C. Bollapalli	[77] [86] [87] [90] [96] [107] [115]
10	Robert K. Brayton	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [15]
11	Victor H. Cordero Calle	[66] [80]
12	Scott J. Campbell	[45]
13	Mosong Cheng	[73]
14	Szu-Tsung Cheng	[3] [5]
15	Gwan S. Choi (Gwan Choi)	[42] [79] [83]
16	Jeff L. Cobb	[50] [97]
17	C. Coelho	[2]
18	John F. Croix	[94]
19	Van R. Culver	[31]
20	Sabyasachi Das	[11] [13] [56] [58] [59] [61] [62] [63]
21	Rajballav Dash	[83]
22	Sandeep Dhar	[30]
23	Chunjie Duan	[18] [32] [35] [68] [70] [80]
24	Stephen A. Edwards	[3] [5]
25	Sasidharan Ekambavanan	[78]
26	Masahiro Fujita	[1] [2]
27	Bruce Gamache	[43]
28	Rajesh Garg	[33] [37] [38] [42] [43] [46] [50] [64] [65] [67] [69] [71] [73] [74] [76] [77] [78] [79] [83] [84] [86] [87] [88] [89] [90] [93] [96]
29	Zoltan Gingl	[99] [102] [110] [113]
30	Eugene Goldberg (Evguenii I. Goldberg)	[52]
31	Salman Gopalani	[73]
32	Wilsin Gosti	[12]
33	Kanupriya Gulati	[22] [32] [34] [36] [39] [40] [44] [46] [51] [52] [54] [55] [60] [72] [75] [77] [82] [85] [90] [91] [92] [94] [95] [96] [97] [98] [109]
34	Anshul Gupta	[46]
35	Gary D. Hachtel	[3] [5]
36	Tamás Horváth	[99] [100] [110] [113]
37	Jiang Hu	[27]
38	Edward Hursey	[20] [25]
39	Alex Ivanov	[116]
40	Jawahar Jain	[1] [2]
41	Abhijit Jas	[82]
42	Nikhil Jayakumar	[14] [16] [17] [20] [22] [25] [26] [27] [29] [30] [36] [37] [40] [42] [43] [46] [48] [49] [51] [53] [54] [57] [79] [81] [103] [115]
43	Tanuj Jindal	[88]
44	Bradley Johnson	[116]
45	A. Kapoor	[16] [57]
46	Vinay Karkala	[87] [88] [105] [114]
47	Laszlo B. Kish	[99] [100] [101] [102] [107] [110] [113]
48	Sriram C. Krishnan	[4]
49	Yuji Kukimoto	[3] [5]
50	Rajesh Kumar	[86] [88] [104]
51	Brock J. LaMeres	[23] [24] [28] [41] [44]
52	Travis Lacour	[105]
53	Stefan Laendner	[48]
54	Peng Li	[27] [64] [92]
55	Pey-Chang Kent Lin	[108] [112] [116] [118] [119]
56	M. Lovell	[34]
57	Dumezie Maduike	[38]
58	Rabi N. Mahapatra	[25] [114] [115] [117]
59	Gagandeep Mallarapu	[67]
60	Ayan Mandal	[112] [114] [115] [117] [119] [120]
61	Patrick McGuinness	[27]
62	Kenneth L. McMillan	[4]
63	Amit Mehrotra	[8]
64	Eric Menendez	[38]
65	Olgica Milenkovic	[48]
66	Vijay Nagarajan	[48]
67	Charu Nagpal	[69] [71]
68	Amit Narayan	[1] [2] [4]
69	Krishna R. Narayanan	[78]
70	Ralph H. J. M. Otten	[8]
71	Abelardo Pardo	[3] [5]
72	Srinivas Patil	[82]
73	Suganth Paul	[74] [81] [82] [84]
74	Ferdinand Peper	[99] [101] [110] [113]
75	Shaz Qadeer	[3] [5]
76	Anand Rajaram	[27]
77	Rajeev K. Ranjan	[3] [5]
78	Nikhil Saluja	[19] [21] [60]
79	Mario Sanchez	[46]
80	Edgar Sánchez-Sinencio	[111]
81	Alberto L. Sangiovanni-Vincentelli	[1] [2] [3] [4] [5] [6] [8] [9] [10] [12] [15]
82	Shaker Sarwary	[3] [5]
83	Serap A. Savari	[106]
84	Rahm Shastry	[94]
85	Bo Shen	[47]
86	Weiping Shi	[39] [55]
87	Thomas R. Shiple	[3] [5]
88	Subarnarekha Sinha	[9] [15]
89	Fabio Somenzi	[3] [5]
90	Tarun Soni	[86]
91	Alexander Sprintson (Alex Sprintson)	[40]
92	Gitanjali Swamy	[3] [5]
93	Didem Zeliha Turker	[111]
94	Sheila Vaidya	[84]
95	Ganesh Venkataraman	[27]
96	Arunprasad Venkatraman	[76]
97	Tiziano Villa	[3] [5]
98	Mandar Waghmode	[39] [55]
99	D. M. H. Walker (Duncan M. Hank Walker)	[54]
100	Joseph Wanstrath	[105]
101	Chengyu Zhu	[70]
102	Takis Zourntos	[47]

Colors in the list of coauthors

Last update Fri Jun 1 15:44:53 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page