Jitendra Khare

	2006
17		Jitendra Khare, Amit B. Shah, Ashok Raman, Girish Rayas: Embedded Memory Field Returns - Trials and Tribulations. ITC 2006: 1-6
	2004
16		Jitendra Khare: Memory Yield Improvement - SoC Design Perspective. ITC 2004: 1445
15		Hans T. Heineken, Jitendra Khare: Test Strategies For a 40Gbps Framer SoC. ITC 2004: 758-763
	2003
14		Jitendra Khare: DFM - A Fabless Perspective. ITC 2003: 1317
	2001
13		John T. Chen, Jitendra Khare, Ken Walker, Saghir A. Shaikh, Janusz Rajski, Wojciech Maly: Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring. ITC 2001: 258-267
12		John T. Chen, Wojciech Maly, Janusz Rajski, Omar Kebichi, Jitendra Khare: Enabling Embedded Memory Diagnosis via Test Response Compression. VTS 2001: 292-298
	2000
11		Jitendra Khare, Hans T. Heineken, M. d'Abreu: Cost Trade-Offs in System On Chip Designs. VLSI Design 2000: 178-184
10		Saghir A. Shaikh, Jitendra Khare, Hans T. Heineken: Manufacturability and Testability Oriented Synthesis. VLSI Design 2000: 185-191
9		Charles H. Ouyang, Hans T. Heineken, Jitendra Khare, Saghir A. Shaikh, M. d'Abreu: Maximizing Wafer Productivity Through Layout Optimization. VLSI Design 2000: 192-197
8		A. Bommireddy, Jitendra Khare, Saghir A. Shaikh, S.-T. Su: Test and Debug of Networking SoCs: A Case Study. VTS 2000: 121-126
	1998
7		Wojciech Maly, Pranab K. Nag, Hans T. Heineken, Jitendra Khare: Design-Manufacturing Interface: Part I - Vision. DATE 1998: 550-556
6		Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Hans T. Heineken, Jitendra Khare, P. Simon: Design-Manufacturing Interface: Part II - Applications. DATE 1998: 557-562
	1997
5		Hans T. Heineken, Jitendra Khare, Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Witold A. Pleskacz: CAD at the Design-Manufacturing Interface. DAC 1997: 321-326
	1996
4		Wojciech Maly, Hans T. Heineken, Jitendra Khare, Pranab K. Nag: Design for manufacturability in submicron domain. ICCAD 1996: 690-697
3		Jitendra Khare, Wojciech Maly, Nathan Tiday: Fault characterization of standard cell libraries using inductive contamination. VTS 1996: 405-413
	1995
2		Jitendra Khare, Wojciech Maly: Inductive Contamination Analysis (ICA) with SRAM Application. ITC 1995: 552-560
1		Jitendra Khare, Sujoy Mitra, Pranab K. Nag, U. Maly, Rob A. Rutenbar: Testability-oriented channel routing. VLSI Design 1995: 208-213

Coauthor Index

1	A. Bommireddy	[8]
2	John T. Chen	[12] [13]
3	Hans T. Heineken	[4] [5] [6] [7] [9] [10] [11] [15]
4	Omar Kebichi	[12]
5	U. Maly	[1]
6	Wojciech Maly	[2] [3] [4] [5] [6] [7] [12] [13]
7	Sujoy Mitra	[1]
8	Pranab K. Nag	[1] [4] [5] [6] [7]
9	Charles H. Ouyang	[5] [6] [9]
10	Witold A. Pleskacz	[5]
11	Janusz Rajski	[12] [13]
12	Ashok Raman	[17]
13	Girish Rayas	[17]
14	Rob A. Rutenbar	[1]
15	Amit B. Shah	[17]
16	Saghir A. Shaikh	[8] [9] [10] [13]
17	P. Simon	[6]
18	S.-T. Su	[8]
19	Nathan Tiday	[3]
20	Ken Walker	[13]
21	M. d'Abreu	[9] [11]

Colors in the list of coauthors

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