Omer Khan

	2012
19		Pengju Ren, Mieszko Lis, Myong Hyon Cho, Keun Sup Shim, Christopher W. Fletcher, Omer Khan, Nanning Zheng, Srinivas Devadas: HORNET: A Cycle-Level Multicore Simulator. IEEE Trans. on CAD of Integrated Circuits and Systems 31(6): 890-903 (2012)
	2011
18		Omer Khan, Henry Hoffmann, Mieszko Lis, Farrukh Hijaz, Anant Agarwal, Srinivas Devadas: ARCc: A case for an architecturally redundant cache-coherence architecture for large multicores. ICCD 2011: 411-418
17		Mieszko Lis, Pengju Ren, Myong Hyon Cho, Keun Sup Shim, Christopher W. Fletcher, Omer Khan, Srinivas Devadas: Scalable, accurate multicore simulation in the 1000-core era. ISPASS 2011: 175-185
16		Myong Hyon Cho, Keun Sup Shim, Mieszko Lis, Omer Khan, Srinivas Devadas: Deadlock-free fine-grained thread migration. NOCS 2011: 33-40
15		Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu, Omer Khan: Performance Per Watt Benefits of Dynamic Core Morphing in Asymmetric Multicores. PACT 2011: 121-130
14		Michel A. Kinsy, Omer Khan, Ivan Celanovic, Dusan Majstorovic, Nikola Celanovic, Srinivas Devadas: Time-Predictable Computer Architecture for Cyber-Physical Systems: Digital Emulation of Power Electronics Systems. RTSS 2011: 305-316
13		Mieszko Lis, Keun Sup Shim, Myong Hyon Cho, Christopher W. Fletcher, Michel A. Kinsy, Ilia A. Lebedev, Omer Khan, Srinivas Devadas: Brief announcement: distributed shared memory based on computation migration. SPAA 2011: 253-256
12		Omer Khan, Mieszko Lis, Yildiz Sinangil, Srinivas Devadas: DCC: A Dependable Cache Coherence Multicore Architecture. Computer Architecture Letters 10(1): 12-15 (2011)
11		Omer Khan, Sandip Kundu: Hardware/Software Codesign Architecture for Online Testing in Chip Multiprocessors. IEEE Trans. Dependable Sec. Comput. 8(5): 714-727 (2011)
10		Omer Khan, Sandip Kundu: Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors. T. HiPEAC 4: 84-110 (2011)
	2010
9		Omer Khan, Sandip Kundu: A model to exploit power-performance efficiency in superscalar processors via structure resizing. ACM Great Lakes Symposium on VLSI 2010: 215-220
8		Omer Khan, Sandip Kundu: A self-adaptive scheduler for asymmetric multi-cores. ACM Great Lakes Symposium on VLSI 2010: 397-400
7		Rance Rodrigues, Sandip Kundu, Omer Khan: Shadow checker (SC): A low-cost hardware scheme for online detection of faults in small memory structures of a microprocessor. ITC 2010: 219-228
6		Omer Khan, Sandip Kundu: Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors. IEEE Trans. Computers 59(5): 651-665 (2010)
	2009
5		Abhisek Pan, Omer Khan, Sandip Kundu: Improving yield and reliability of chip multiprocessors. DATE 2009: 490-495
4		Omer Khan, Sandip Kundu: A self-adaptive system architecture to address transistor aging. DATE 2009: 81-86
3		Omer Khan, Sandip Kundu: Hardware/software co-design architecture for thermal management of chip multiprocessors. DATE 2009: 952-957
2		Omer Khan, Sandip Kundu: Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines. HiPEAC 2009: 293-307
	2008
1		Omer Khan, Sandip Kundu: A framework for predictive dynamic temperature management of microprocessor systems. ICCAD 2008: 258-263

Coauthor Index

1	Anant Agarwal	[18]
2	Arunachalam Annamalai	[15]
3	Ivan Celanovic	[14]
4	Nikola Celanovic	[14]
5	Myong Hyon Cho	[13] [16] [17] [19]
6	Srinivas Devadas	[12] [13] [14] [16] [17] [18] [19]
7	Christopher W. Fletcher	[13] [17] [19]
8	Farrukh Hijaz	[18]
9	Henry Hoffmann (Hank Hoffmann)	[18]
10	Michel A. Kinsy	[13] [14]
11	Israel Koren	[15]
12	Sandip Kundu	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [15]
13	Ilia A. Lebedev	[13]
14	Mieszko Lis	[12] [13] [16] [17] [18] [19]
15	Dusan Majstorovic	[14]
16	Abhisek Pan	[5]
17	Pengju Ren	[17] [19]
18	Rance Rodrigues	[7] [15]
19	Keun Sup Shim	[13] [16] [17] [19]
20	Yildiz Sinangil	[12]
21	Nanning Zheng	[19]

Colors in the list of coauthors

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