 | 2012 |
|---|
| 10 |       | Brian Keng,
Andreas G. Veneris:
Path directed abstraction and refinement in SAT-based design debugging.
DAC 2012: 947-954 |
| 9 | | Bao Le,
Hratch Mangassarian,
Brian Keng,
Andreas G. Veneris:
Non-solution implications using reverse domination in a modern SAT-based debugging environment.
DATE 2012: 629-634 |
| 2011 |
|---|
| 8 | | Andreas G. Veneris,
Brian Keng,
Sean Safarpour:
From RTL to silicon: The case for automated debug.
ASP-DAC 2011: 306-310 |
| 7 | | Brian Keng,
Andreas G. Veneris:
Managing complexity in design debugging with sequential abstraction and refinement.
ASP-DAC 2011: 479-484 |
| 6 | | Brian Keng,
Sean Safarpour,
Andreas G. Veneris:
Automated debugging of SystemVerilog assertions.
DATE 2011: 323-328 |
| 2010 |
|---|
| 5 | | Yu-Shen Yang,
Brian Keng,
Nicola Nicolici,
Andreas G. Veneris,
Sean Safarpour:
Automated silicon debug data analysis techniques for a hardware data acquisition environment.
ISQED 2010: 675-682 |
| 4 | | Brian Keng,
Andreas G. Veneris,
Sean Safarpour:
An Automated Framework for Correction and Debug of PSL Assertions.
MTV 2010: 9-12 |
| 3 | | Brian Keng,
Sean Safarpour,
Andreas G. Veneris:
Bounded Model Debugging.
IEEE Trans. on CAD of Integrated Circuits and Systems 29(11): 1790-1803 (2010) |
| 2009 |
|---|
| 2 | | Brian Keng,
Andreas G. Veneris:
Scaling VLSI design debugging with interpolation.
FMCAD 2009: 144-151 |
| 2008 |
|---|
| 1 | | Brian Keng,
Hratch Mangassarian,
Andreas G. Veneris:
A succinct memory model for automated design debugging.
ICCAD 2008: 137-142 |
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