 | 2011 |
| 10 |  | Shinichi Moriwaki,
Atsushi Kawasumi,
Toshikazu Suzuki,
Takayasu Sakurai,
Shinji Miyano:
0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme.
CICC 2011: 1-4 |
| 9 |  | Yu Pu,
Xin Zhang,
Katsuyuki Ikeuchi,
Atsushi Muramatsu,
Atsushi Kawasumi,
Makoto Takamiya,
Masahiro Nomura,
Hirofumi Shinohara,
Takayasu Sakurai:
Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits.
IEEE Trans. on Circuits and Systems 58-II(5): 294-298 (2011) |
| 8 |  | Yusuke Niki,
Atsushi Kawasumi,
Azuma Suzuki,
Yasuhisa Takeyama,
Osamu Hirabayashi,
Keiichi Kushida,
Fumihiko Tachibana,
Yuki Fujimura,
Tomoaki Yabe:
A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers.
J. Solid-State Circuits 46(11): 2545-2551 (2011) |
| 2010 |
| 7 |  | Yuki Fujimura,
Osamu Hirabayashi,
Takahiko Sasaki,
Azuma Suzuki,
Atsushi Kawasumi,
Yasuhisa Takeyama,
Keiichi Kushida,
Gou Fukano,
Akira Katayama,
Yusuke Niki,
Tomoaki Yabe:
A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm2 cell in 32nm high-k metal-gate CMOS.
ISSCC 2010: 348-349 |
| 6 |  | Atsushi Kawasumi,
Yasuhisa Takeyama,
Osamu Hirabayashi,
Keiichi Kushida,
Yuki Fujimura,
Tomoaki Yabe:
A Low-Supply-Voltage-Operation SRAM With HCI Trimmed Sense Amplifiers.
J. Solid-State Circuits 45(11): 2341-2347 (2010) |
| 2009 |
| 5 |  | Osamu Hirabayashi,
Atsushi Kawasumi,
Azuma Suzuki,
Yasuhisa Takeyama,
Keiichi Kushida,
Takahiko Sasaki,
Akira Katayama,
Gou Fukano,
Yuki Fujimura,
Takaaki Nakazato,
Yasushi Shizuki,
Natsuki Kushiyama,
Tomoaki Yabe:
A process-variation-tolerant dual-power-supply SRAM with 0.179µm2 Cell in 40nm CMOS using level-programmable wordline driver.
ISSCC 2009: 458-459 |
| 2007 |
| 4 |  | Brian K. Flachs,
Shigehiro Asano,
Sang H. Dhong,
H. Peter Hofstee,
Gilles Gervais,
Roy Kim,
Tien Le,
Peichun Liu,
Jens Leenstra,
John S. Liberty,
Brad W. Michael,
Hwa-Joon Oh,
Silvia M. Müller,
Osamu Takahashi,
Koji Hirairi,
Atsushi Kawasumi,
Hiroaki Murakami,
Hiromi Noro,
Shoji Onishi,
Juergen Pille,
Joel Silberman,
Suksoon Yong,
Akiyuki Hatakeyama,
Yukio Watanabe,
Naoka Yano,
Daniel A. Brokenshire,
Mohammad Peyravian,
VanDung To,
Eiji Iwata:
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI.
IBM Journal of Research and Development 51(5): 529-544 (2007) |
| 2005 |
| 3 |  | Osamu Takahashi,
Russ Cook,
Scott R. Cottier,
Sang H. Dhong,
Brian K. Flachs,
Koji Hirairi,
Atsushi Kawasumi,
Hiroaki Murakami,
Hiromi Noro,
Hwa-Joon Oh,
S. Onish,
Juergen Pille,
Joel Silberman:
The circuit design of the synergistic processor element of a CELL processor.
ICCAD 2005: 111-117 |
| 2 |  | Toru Asano,
Joel Silberman,
Sang H. Dhong,
Osamu Takahashi,
Michael White,
Scott R. Cottier,
Takaaki Nakazato,
Atsushi Kawasumi,
Hiroshi Yoshihara:
Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell Processor.
IEEE Micro 25(5): 30-38 (2005) |
| 2002 |
| 1 |  | Osamu Hirabayashi,
Azuma Suzuki,
Tomoaki Yabe,
Atsushi Kawasumi,
Yasuhisa Takeyama,
Keiichi Kushida,
A. Tohata,
Nobuaki Otsuka:
DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs.
ITC 2002: 164-169 |