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Atsushi Kawasumi Coauthor index pubzone.org

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DBLP keys2011
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLShinichi Moriwaki, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Shinji Miyano: 0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme. CICC 2011: 1-4
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYu Pu, Xin Zhang, Katsuyuki Ikeuchi, Atsushi Muramatsu, Atsushi Kawasumi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai: Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits. IEEE Trans. on Circuits and Systems 58-II(5): 294-298 (2011)
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYusuke Niki, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yuki Fujimura, Tomoaki Yabe: A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers. J. Solid-State Circuits 46(11): 2545-2551 (2011)
2010
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYuki Fujimura, Osamu Hirabayashi, Takahiko Sasaki, Azuma Suzuki, Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, Gou Fukano, Akira Katayama, Yusuke Niki, Tomoaki Yabe: A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm2 cell in 32nm high-k metal-gate CMOS. ISSCC 2010: 348-349
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAtsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Yuki Fujimura, Tomoaki Yabe: A Low-Supply-Voltage-Operation SRAM With HCI Trimmed Sense Amplifiers. J. Solid-State Circuits 45(11): 2341-2347 (2010)
2009
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLOsamu Hirabayashi, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Keiichi Kushida, Takahiko Sasaki, Akira Katayama, Gou Fukano, Yuki Fujimura, Takaaki Nakazato, Yasushi Shizuki, Natsuki Kushiyama, Tomoaki Yabe: A process-variation-tolerant dual-power-supply SRAM with 0.179µm2 Cell in 40nm CMOS using level-programmable wordline driver. ISSCC 2009: 458-459
2007
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLBrian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia M. Müller, Osamu Takahashi, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Shoji Onishi, Juergen Pille, Joel Silberman, Suksoon Yong, Akiyuki Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, VanDung To, Eiji Iwata: Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI. IBM Journal of Research and Development 51(5): 529-544 (2007)
2005
3no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLOsamu Takahashi, Russ Cook, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Hwa-Joon Oh, S. Onish, Juergen Pille, Joel Silberman: The circuit design of the synergistic processor element of a CELL processor. ICCAD 2005: 111-117
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLToru Asano, Joel Silberman, Sang H. Dhong, Osamu Takahashi, Michael White, Scott R. Cottier, Takaaki Nakazato, Atsushi Kawasumi, Hiroshi Yoshihara: Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell Processor. IEEE Micro 25(5): 30-38 (2005)
2002
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLOsamu Hirabayashi, Azuma Suzuki, Tomoaki Yabe, Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, A. Tohata, Nobuaki Otsuka: DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs. ITC 2002: 164-169

Coauthor Index

1Shigehiro Asano [4]
2Toru Asano [2]
3Daniel A. Brokenshire [4]
4Russ Cook [3]
5Scott R. Cottier [2] [3]
6Sang H. Dhong [2] [3] [4]
7Brian K. Flachs [3] [4]
8Yuki Fujimura [5] [6] [7] [8]
9Gou Fukano [5] [7]
10Gilles Gervais [4]
11Akiyuki Hatakeyama [4]
12Osamu Hirabayashi [1] [5] [6] [7] [8]
13Koji Hirairi [3] [4]
14H. Peter Hofstee [4]
15Katsuyuki Ikeuchi [9]
16Eiji Iwata [4]
17Akira Katayama [5] [7]
18Roy Kim [4]
19Keiichi Kushida [1] [5] [6] [7] [8]
20Natsuki Kushiyama [5]
21Tien Le [4]
22Jens Leenstra [4]
23John S. Liberty [4]
24Peichun Liu [4]
25Brad W. Michael [4]
26Shinji Miyano [10]
27Shinichi Moriwaki [10]
28Silvia M. Müller (Silvia Melitta Müller) [4]
29Hiroaki Murakami [3] [4]
30Atsushi Muramatsu [9]
31Takaaki Nakazato [2] [5]
32Yusuke Niki [7] [8]
33Masahiro Nomura [9]
34Hiromi Noro [3] [4]
35Hwa-Joon Oh [3] [4]
36S. Onish [3]
37Shoji Onishi [4]
38Nobuaki Otsuka [1]
39Mohammad Peyravian [4]
40Juergen Pille (Jürgen Pille) [3] [4]
41Yu Pu [9]
42Takayasu Sakurai [9] [10]
43Takahiko Sasaki [5] [7]
44Hirofumi Shinohara [9]
45Yasushi Shizuki [5]
46Joel Silberman [2] [3] [4]
47Azuma Suzuki [1] [5] [7] [8]
48Toshikazu Suzuki [10]
49Fumihiko Tachibana [8]
50Osamu Takahashi [2] [3] [4]
51Makoto Takamiya [9]
52Yasuhisa Takeyama [1] [5] [6] [7] [8]
53VanDung To [4]
54A. Tohata [1]
55Yukio Watanabe [4]
56Michael White [2]
57Tomoaki Yabe [1] [5] [6] [7] [8]
58Naoka Yano [4]
59Suksoon Yong [4]
60Hiroshi Yoshihara [2]
61Xin Zhang [9]

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