 | 2007 |
|---|
| 5 |       | Yuuri Sugihara,
Manabu Kotani,
Kazuya Katsuki,
Kazutoshi Kobayashi,
Hidetoshi Onodera:
A 90nm 8×16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations.
ASP-DAC 2007: 122-123 |
| 4 | | Kazutoshi Kobayashi,
Kazuya Katsuki,
Manabu Kotani,
Yuuri Sugihara,
Yohei Kume,
Hidetoshi Onodera:
A 90 nm 48 x 48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations.
IEICE Transactions 90-C(10): 1919-1926 (2007) |
| 3 | | Kazuya Katsuki,
Manabu Kotani,
Kazutoshi Kobayashi,
Hidetoshi Onodera:
A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations.
IEICE Transactions 90-C(4): 699-707 (2007) |
| 2006 |
|---|
| 2 | | Kazuya Katsuki,
Manabu Kotani,
Kazutoshi Kobayashi,
Hidetoshi Onodera:
Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices.
ASP-DAC 2006: 110-111 |
| 1 | | Kazutoshi Kobayashi,
Manabu Kotani,
Kazuya Katsuki,
Y. Takatsukasa,
K. Ogata,
Yuuri Sugihara,
Hidetoshi Onodera:
A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime.
FPL 2006: 1-4 |
Data released under the ODC-BY 1.0 license — See also our legal information page