 | 2011 |
|---|
| 10 |       | Nirav Dave,
Michael Katelman,
Myron King,
Arvind,
José Meseguer:
Verification of microarchitectural refinements in rule-based systems.
MEMOCODE 2011: 61-71 |
| 2010 |
|---|
| 9 | | Michael Katelman,
José Meseguer:
vlogsl: A Strategy Language for Simulation-Based Verification of Hardware.
Haifa Verification Conference 2010: 129-145 |
| 8 | | Patrick O'Neil Meredith,
Michael Katelman,
José Meseguer,
Grigore Rosu:
A formal executable semantics of Verilog.
MEMOCODE 2010: 179-188 |
| 7 | | Michael Katelman,
José Meseguer:
Using the PALS Architecture to Verify a Distributed Topology Control Protocol for Wireless Multi-Hop Networks in the Presence of Node Failures
RTRTS 2010: 101-116 |
| 6 | | Michael Katelman,
Sean Keller,
José Meseguer:
Concurrent Rewriting Semantics and Analysis of Asynchronous Digital Circuits.
WRLA 2010: 140-156 |
| 2008 |
|---|
| 5 | | Arvind,
Nirav Dave,
Michael Katelman:
Getting Formal Verification into Design Flow.
FM 2008: 12-32 |
| 4 | | Michael Katelman,
José Meseguer,
Jennifer C. Hou:
Redesign of the LMST Wireless Sensor Protocol through Formal Modeling and Statistical Model Checking.
FMOODS 2008: 150-169 |
| 3 | | Michael Katelman,
José Meseguer,
Santiago Escobar:
Directed-Logical Testing for Functional Verification of Microprocessors.
MEMOCODE 2008: 89-100 |
| 2007 |
|---|
| 2 | | Michael Katelman,
José Meseguer:
A Rewriting Semantics for ABEL with Applications to Hardware/Software Co-Design and Analysis.
Electr. Notes Theor. Comput. Sci. 176(4): 47-60 (2007) |
| 2006 |
|---|
| 1 | | Sam Kamin,
Baris Aktemur,
Michael Katelman:
Staging static analyses for program generation.
GPCE 2006: 1-10 |
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